Aceshardware

Hans de Vries · Joined: 07 Aug 2007 Posts: 74

Paul DeMone wrote:

Hans de Vries wrote:

The PS3 cell processor was ported from 65nm to 45nm resulting
in either a 40% improvement in power consumption or a 20%
improvement in frequency.

This is using IBM's 45nm SOI process so the scaling for AMD's
Deneb could yield similar results.

Paul DeMone wrote:

What is the relative die area and transistor count between the 65
and 45 nm Cell?

Cell core goes from 11.08 mm2 at 65nm to 6.47 mm2 at 45nm (100 --> 58.5%)
Power core goes from 19.60 mm2 at 65nm to 11.32 mm2 at 45nm (100 --> 57.7%)

Paul DeMone wrote:

What is the relative die area and transistor count between the 65
and 45 nm K8L?

K10 core goes from 25.5 mm2 at 65nm to 15 mm2 at 45nm (100 --> 59%)

Paul DeMone wrote:

Do you think AMD and IBM use identical processes at each feature
size?

Parameters (e.g. Tox) will differ. Basic "ingredients" will be the same.

Regards, Hans

Paul DeMone · Joined: 29 Aug 2007 Posts: 376 Location: Great white north

Hans de Vries wrote:

Paul DeMone wrote:

Hans de Vries wrote:

The PS3 cell processor was ported from 65nm to 45nm resulting
in either a 40% improvement in power consumption or a 20%
improvement in frequency.

This is using IBM's 45nm SOI process so the scaling for AMD's
Deneb could yield similar results.

Paul DeMone wrote:

What is the relative die area and transistor count between the 65
and 45 nm Cell?

Cell core goes from 11.08 mm2 at 65nm to 6.47 mm2 at 45nm (100 --> 58.5%)
Power core goes from 19.60 mm2 at 65nm to 11.32 mm2 at 45nm (100 --> 57.7%)

Paul DeMone wrote:

What is the relative die area and transistor count between the 65
and 45 nm K8L?

K10 core goes from 25.5 mm2 at 65nm to 15 mm2 at 45nm (100 --> 59%)

Paul DeMone wrote:

Do you think AMD and IBM use identical processes at each feature
size?

Parameters (e.g. Tox) will differ. Basic "ingredients" will be the same.

Regards, Hans

Core statistics are utterly irrelevent to the issues at hand. I suspect you
already knew that given the way you pretended to answer my questions
but didn't in order to save your fallacious analogy between 65 and 45 nm
Cell and K8L.

no@spam.com · Joined: 07 Oct 2007 Posts: 53

> Core statistics are utterly irrelevent to the issues at hand. I suspect you
> already knew that given the way you pretended to answer my questions
> but didn't in order to save your fallacious analogy between 65 and 45 nm
> Cell and K8L.

Pray educate us with your numbers then!

Hans de Vries · Joined: 07 Aug 2007 Posts: 74

Paul DeMone wrote:

your fallacious analogy between 65 and 45 nm
Cell and K8L.

As every friendly Intel engineer would advice you:

The improvements in PS3 characteristics due to the migration from
65nm to 45nm IBM/AMD co-developed SOI processes provides one of
the better opportunities to asses potential Shanghai characteristics
even though IBM and AMD tweak their processes a bit for their own
purpose.

Regards, Hans

Paul DeMone · Joined: 29 Aug 2007 Posts: 376 Location: Great white north

no@spam.com wrote:

> Core statistics are utterly irrelevent to the issues at hand. I suspect you
> already knew that given the way you pretended to answer my questions
> but didn't in order to save your fallacious analogy between 65 and 45 nm
> Cell and K8L.

Pray educate us with your numbers then!

The Cell shrink devices involved effectively a fixed design and fixed
target frequency (the Cell variant for HPC is a different matter) with
the primary goals of cost and power reductions. The die size shrinks
as appropriately given the non-scaling aspect of the I/O regions and
the lack of need to scale frequency allows circuit optimizations within
each shrink to enhance power savings. Die size is reduced by about
a third and TDP by a reported 38%.

The K8L shrink involves the tripling of L3 capacity and significant
competitive pressure to raise clock rates over the 65 nm version.
Transistor count is increased by about half again and die size
reduction is likely on the order of 15%. AMD will be on the knife
edge to balance the minimal process advantage of 45 nm between
lower TDP and better yield in the higher frequency bins.

Paul DeMone · Joined: 29 Aug 2007 Posts: 376 Location: Great white north

Hans de Vries wrote:

Paul DeMone wrote:

your fallacious analogy between 65 and 45 nm
Cell and K8L.

As every friendly Intel engineer would advice you:

The improvements in PS3 characteristics due to the migration from
65nm to 45nm IBM/AMD co-developed SOI processes provides one of
the better opportunities to asses potential Shanghai characteristics
even though IBM and AMD tweak their processes a bit for their own
purpose.

Engineers use models and scaling techniques but spend much effort to
understand their limitations and pitfalls. Enthusiasts use analogies and
hand waving but spend much effort in data selection to fit their hopes
and dreams. Engineers see trade-offs. Enthusiasts see all-you-can-eat
buffets.

Hans de Vries · Joined: 07 Aug 2007 Posts: 74

Paul DeMone wrote:

The K8L shrink involves the tripling of L3 capacity and significant
competitive pressure to raise clock rates over the 65 nm version..

The 24 MB cache of Montecito at 90nm dissipates a mere 5 Watts under
load. The extra 4MB of Shanghai at 45nm will have a minimal impact for
the total power dissipation using standard power reduction strategies.

There is no interrelation between core speed and cache power since
they have separated power supplies.

Paul DeMone wrote:

Transistor count is increased by about half again and die size
reduction is likely on the order of 15%..

Transistor count increase is all from the cache... In Montecito 95%
of the chips transistors are from the cache while they dissipate only
5% of the total power....

Paul DeMone wrote:

AMD will be on the knife
edge to balance the minimal process advantage of 45 nm between
lower TDP and better yield in the higher frequency bins.

Next time show some facts instead of Lyrics. Bye now.

Regards, Hans

Paul DeMone · Joined: 29 Aug 2007 Posts: 376 Location: Great white north

Hans de Vries wrote:

Paul DeMone wrote:

The K8L shrink involves the tripling of L3 capacity and significant
competitive pressure to raise clock rates over the 65 nm version..

The 24 MB cache of Montecito at 90nm dissipates a mere 5 Watts under
load. The extra 4MB of Shanghai at 45nm will have a minimal impact for
the total power dissipation using standard power reduction strategies.

There is no interrelation between core speed and cache power since
they have separated power supplies.

Paul DeMone wrote:

Transistor count is increased by about half again and die size
reduction is likely on the order of 15%..

Transistor count increase is all from the cache... As in Montecito 95%
of the chips transistors are from the cache while they dissipate only
5% of the total power....

Paul DeMone wrote:

AMD will be on the knife
edge to balance the minimal process advantage of 45 nm between
lower TDP and better yield in the higher frequency bins.

Next time show some facts instead of Lyrics. Bye now.

Regards, Hans

Once again you show a little knowledge is a dangerous thing,
thus reinforcing my reply to your last post. :-P

1) The Montecito is a 90 nm processor and Shanghai is a 45 nm
chip. At 90nm Vcache < Vcore to reduce leakage and dynamic
power in the cache. At 45 nm Vcache is almost always > Vcore
to improve cell noise margin and data stability. Oooops!

2) The Montecito L3 consists of two distinct and separate halves,
each half servicing only one core with its 1.25 MB of L2 reducing
traffic to each half of the L3. The Shanghai uses a single unified
L3 servicing traffic from four cores with only a 0.5 MB L2 reducing
traffic between each core and the L3. Activity factor and power
dissipation? well gosh!

3) Your 5 W 24 MB cache at 90 nm becomes a 20 W 24 MB cache
at 65 nm. Care to extrapolate what happens to the cache power
dissipation trend at 45 nm without hk/mg?

Hans de Vries · Joined: 07 Aug 2007 Posts: 74

Paul DeMone wrote:

Once again you show a little knowledge is a dangerous thing,
thus reinforcing my reply to your last post. :-P

1) The Montecito is a 90 nm processor and Shanghai is a 45 nm
chip. At 90nm Vcache < Vcore to reduce leakage and dynamic
power in the cache. At 45 nm Vcache is almost always > Vcore
to improve cell noise margin and data stability. Oooops!

2) The Montecito L3 consists of two distinct and separate halves,
each half servicing only one core with its 1.25 MB of L2 reducing
traffic to each half of the L3. The Shanghai uses a single unified
L3 servicing traffic from four cores with only a 0.5 MB L2 reducing
traffic between each core and the L3. Activity factor and power
dissipation? well gosh!

3) Your 5 W 24 MB cache at 90 nm becomes a 20 W 24 MB cache
at 65 nm. Care to extrapolate what happens to the cache power
dissipation trend at 45 nm without hk/mg?

I can't believe I'm still reacting to your posts....

A number of trivialities and a doomsday scenario don't add up.

As long as IBM manages to cut power consumption of it's non-HKMG
45nm SRAM macros by well over 50% compared to it's previous
generation SRAM and TSMC has implemented 32nm non-HKMG SRAM
which it plans to use for digital camera and HD-camcorder clients.

Regards, Hans

no@spam.com · Joined: 07 Oct 2007 Posts: 53

> 1) The Montecito is a 90 nm processor and Shanghai is a 45 nm
> chip. At 90nm Vcache < Vcore to reduce leakage and dynamic
> power in the cache. At 45 nm Vcache is almost always > Vcore
> to improve cell noise margin and data stability. Oooops!

Looks like you are one of those amateurs then, rather than an
engineer with access to C0/C1 documentation/samples. So far
they all have V_NB =< V_CORE.

> 2) The Montecito L3 consists of two distinct and separate halves,
> each half servicing only one core with its 1.25 MB of L2 reducing
> traffic to each half of the L3. The Shanghai uses a single unified
> L3 servicing traffic from four cores with only a 0.5 MB L2 reducing
> traffic between each core and the L3. Activity factor and power
> dissipation? well gosh!

The K8L L3 is composed of two arrays. As an engineer you can
see this, if you throw the the right code at it.

> 3) Your 5 W 24 MB cache at 90 nm becomes a 20 W 24 MB cache
> at 65 nm. Care to extrapolate what happens to the cache power
> dissipation trend at 45 nm [u]without hk/mg?

Well, the 65->45 transition enabled 2->6 MB L3, HT1->HT3, and
slightly higher frequencies... while remaining in the same TDP.

dkanter · Joined: 20 Sep 2007 Posts: 53

Paul DeMone wrote:

no@spam.com wrote:

> Core statistics are utterly irrelevent to the issues at hand. I suspect you
> already knew that given the way you pretended to answer my questions
> but didn't in order to save your fallacious analogy between 65 and 45 nm
> Cell and K8L.

Pray educate us with your numbers then!

The Cell shrink devices involved effectively a fixed design and fixed
target frequency (the Cell variant for HPC is a different matter) with
the primary goals of cost and power reductions. The die size shrinks
as appropriately given the non-scaling aspect of the I/O regions and
the lack of need to scale frequency allows circuit optimizations within
each shrink to enhance power savings. Die size is reduced by about
a third and TDP by a reported 38%.

The K8L shrink involves the tripling of L3 capacity and significant
competitive pressure to raise clock rates over the 65 nm version.
Transistor count is increased by about half again and die size
reduction is likely on the order of 15%. AMD will be on the knife
edge to balance the minimal process advantage of 45 nm between
lower TDP and better yield in the higher frequency bins.

The main objective of the cell shrink was to use as little man power as possible. IIRC, the shrink only took around 10 man years to complete at the cost of suboptimal area and power scaling.

DK

LiamC · Joined: 23 Jul 2007 Posts: 70

dkanter wrote:

The main objective of the cell shrink was to use as little man power as possible. IIRC, the shrink only took around 10 man years to complete at the cost of suboptimal area and power scaling.

DK

Where did you hear this? And what was the reason behind such a choice? Everybody working on bulldozer?

Paul DeMone · Joined: 29 Aug 2007 Posts: 376 Location: Great white north

dkanter wrote:

The main objective of the cell shrink was to use as little man power as possible. IIRC, the shrink only took around 10 man years to complete at the cost of suboptimal area and power scaling.

DK

That would be a change in strategy vs the 90 nm to 65 nm shrink.
IBM took the opportunity to use the device performance gain and
more or less fixed target frequency to replace some control logic
in the SPEs that was implemented with dynamic circuitry in 90 nm
to meet the cycle time goal with static circuitry in 65 nm to reduce
power.

No one but no one dicks around changing working control logic let
alone time critical circuit topologies when you are trying to use "as
little manpower as possible". :roll:

inf64 · Joined: 04 Sep 2007 Posts: 58

LiamC wrote:

dkanter wrote:

The main objective of the cell shrink was to use as little man power as possible. IIRC, the shrink only took around 10 man years to complete at the cost of suboptimal area and power scaling.

DK

Where did you hear this? And what was the reason behind such a choice? Everybody working on bulldozer?

Mr. Kanteris obviously speaks of Cell device and not Shanghai(produced by AMD).

Paul DeMone · Joined: 29 Aug 2007 Posts: 376 Location: Great white north

no@spam.com wrote:

> 1) The Montecito is a 90 nm processor and Shanghai is a 45 nm
> chip. At 90nm Vcache < Vcore to reduce leakage and dynamic
> power in the cache. At 45 nm Vcache is almost always > Vcore
> to improve cell noise margin and data stability. Oooops!

Looks like you are one of those amateurs then, rather than an
engineer with access to C0/C1 documentation/samples. So far
they all have V_NB =< V_CORE.

LOL, I am talking about well engineered multi-core chips. If your
claim is true that just shows how intractable AMD's speed path
problems with the K8L core are relative to the frequency targets
imposed by competitive pressures. This would also help explain
the TDP figures associated with Shanghai. :-O

Quote:

> 2) The Montecito L3 consists of two distinct and separate halves,
> each half servicing only one core with its 1.25 MB of L2 reducing
> traffic to each half of the L3. The Shanghai uses a single unified
> L3 servicing traffic from four cores with only a 0.5 MB L2 reducing
> traffic between each core and the L3. Activity factor and power
> dissipation? well gosh!

The K8L L3 is composed of two arrays. As an engineer you can
see this, if you throw the the right code at it.

Two arrays? We obviously aren't even speaking the same language
on the basic technology so it isn't surprising you missed the more
"abstract" point of that comment. BTW, I can't think of any possible
interpretation of your random comment that would in any way
attack my point, and there are some would actually reinforce it.

Quote:

> 3) Your 5 W 24 MB cache at 90 nm becomes a 20 W 24 MB cache
> at 65 nm. Care to extrapolate what happens to the cache power
> dissipation trend at 45 nm [u]without hk/mg?

Well, the 65->45 transition enabled 2->6 MB L3, HT1->HT3, and
slightly higher frequencies... while remaining in the same TDP.

So claims AMD? We all know how well believing in the performance
and power claims for Barcelona made when it was at a similar stage
of development as Shanghai is now worked out.