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Unless I'm mistaken, AMD announced that they were starting 45nm volume production in Q2. The availability of actual products was in November.
Yes it will be available in Q2.Past node ramp and 45nm Deneb schedules have nothing to do with BD. Server BD is Q2 start of production and Q3 availability.This implies that BD desktop production ramp is in early Q2 if it is to make the Q2 launch(assume may or June).
Azazel wrote:
@Dresdenboy. You are right. There were a few engineering samples apparently stolen from labs.
Nothing was stolen from the labs afaik. There were some Magny Cours chips on sale prior to official launch since some online shops jumped the gun early.
Joined: Wed Feb 10, 2010 10:19 am Posts: 499 Location: Moscow, Russia
muziqaz wrote:
Yet again another prophecy based on past events. What about interlagos then? AMD said they start production q2 with available products q3.
Really, you missed my point. Even if Orochi(server) will be really launched in Q3-2011 it will have no effect on AMD server sales in 2011. The reasons behind it are the IT business nature and ramp curve.
And as i told back in 2009, 2010 will be more or less modest but 2011 will be very hard year for AMD. And only God knows what we'll see in 2012.
Yet again another prophecy based on past events. What about interlagos then? AMD said they start production q2 with available products q3.
Really, you missed my point. Even if Orochi(server) will be really launched in Q3-2011 it will have no effect on AMD server sales in 2011. The reasons behind it are the IT business nature and ramp curve.
And as i told back in 2009, 2010 will be more or less modest but 2011 will be very hard year for AMD. And only God knows what we'll see in 2012.
Yes yes,the sky is falling. We've heard that many times before,yet it's still in place,the sky that is.
Joined: Wed Aug 29, 2007 3:55 pm Posts: 1006 Location: Great white north
inf64 wrote:
Azazel wrote:
muziqaz wrote:
Yet again another prophecy based on past events. What about interlagos then? AMD said they start production q2 with available products q3.
Really, you missed my point. Even if Orochi(server) will be really launched in Q3-2011 it will have no effect on AMD server sales in 2011. The reasons behind it are the IT business nature and ramp curve.
And as i told back in 2009, 2010 will be more or less modest but 2011 will be very hard year for AMD. And only God knows what we'll see in 2012.
Yes yes,the sky is falling. We've heard that many times before,yet it's still in place,the sky that is.
When it comes to servers the sky hasn't quite fallen yet for AMD but it is definitely low enough to touch.
Joined: Wed Aug 29, 2007 3:55 pm Posts: 1006 Location: Great white north
inf64 wrote:
The OEMs were just too slow to adopt the platform ,that's all.
ROFL, I think that excuse got stale about a quarter ago.
AMD released MC seven and a half months ago and OEM systems have been available for quite a while. The reality is Intel has more compelling products. AMD knew this would happen and priced MC dirt cheap compared to Xeon but that simply isn't enough to sway the vast majority of buyers.
And as follows from the article, Interlagos has dies stacked up. As i understand it leads to perf degradation of low die. With Turbo, it could be very notable.
And as follows from the article, Interlagos has dies stacked up. As i understand it leads to perf degradation of low die. With Turbo, it could be very notable.
Dude seriously ,lay of the crack pipe... Article does not mention stacked dies for Interlagos. Your understanding of things seems either very limited or purposely skewed.
* The Bulldozer 2-core CPU module contains 213M transistors * 11-Metal layers * Designed to operate from 0.8 to 1.3V * Operates at 3.5GHz+ * 2-Core CPU module die size (including 2MB L2 cache) is 30.9mm2 * 8MB level 3 cache (composed of 4 independent 2MB subcaches) operates above 2.4GHz at 1.1V * 40 Entry unified OOO scheduler * Issues 4 operations per cycle with full single cycle bypass
Quote:
4.5 Design Solutions for the Bulldozer 32nm SOI 2-Core Processor Module in an 8-Core CPU T. Fischer, S. Arekapudi, E. Busta, C. Dietz, M. Golden, S. Hilker, A. Horiuchi, K. A. Hurd, D. Johnson, H. McIntyre, S. Naffziger, J. Vinh, J. White, K. Wilcox, AMD The Bulldozer 2-core CPU module contains 213M transistors in an 11-metal layer 32nm high-k metalgate SOI CMOS process and is designed to operate from 0.8 to 1.3V. This micro-architecture improves performance and frequency while reducing area and power over a previous AMD x86-64 CPU in the same process. The design reduces the number of gates/cycle relative to prior designs, achieving 3.5GHz+ operation in an area (including 2MB L2 cache) of 30.9mm2.
4.6 40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD Bulldozer x86-64 Core M. Golden, S. Arekapudi, J. Vinh, AMD A 40-instruction out-of-order scheduler issues four operations per cycle and supports single-cycle operation wakeup. The integer execution unit supports single-cycle bypass between four functional units. Critical paths are implemented without exotic circuit techniques or heavy reliance on full-custom design. Architectural choices minimize power consumption.
Quote:
14.3 An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing D. Weiss, M. Dreesen, M. Ciraula, C. Henrion, C. Helt, R. Freese, T. Miles, A. Karegar, R. Schreiber, B. Schneller, J. Wuu, AMD An 8MB level 3 cache, composed of 4 independent 2MB subcaches, is built on a 32nm SOI process. It features column-select aliasing to improve area efficiency, supply gating and floating bitlines to reduce leakage power, and centralized redundant row and column blocks to improve yield and testability. The cache operates above 2.4GHz at 1.1V.
JF-AMD confirms (yet again...) that higher single thread performance (than 10h) generation comes from core level changes(IPC) and that new Turbo comes on top of that: http://www.amdzone.com/phpbb3/viewtopic ... 38#p193838
Quote:
All of the single thread advantages are without turbo mode. Turbo only makes it better.
Yes, we have said in public that IPC would be higher and single threaded performance will be higher. Anyone saying otherwise is either uninformed, or has a specific agenda.
Joined: Wed Aug 29, 2007 3:55 pm Posts: 1006 Location: Great white north
JF-AMD wrote:
Yes, we have said in public that IPC would be higher and single threaded performance will be higher. Anyone saying otherwise is either uninformed, or has a specific agenda.
Have you and/or AMD ever stated that single thread IPC would be higher?
Joined: Wed Feb 10, 2010 10:19 am Posts: 499 Location: Moscow, Russia
inf64 wrote:
JF-AMD confirms (yet again...) that higher single thread performance (than 10h) generation comes from core level changes(IPC) and that new Turbo comes on top of that: http://www.amdzone.com/phpbb3/viewtopic ... 38#p193838
Of course, it should be higher. Nobody argues this. Even AMD publicly stated "up to 50% more int performance with 33% more cores". The questions which are left are a) how much of it comes from much bigger cache and how much from architecture tuning and b) Is that ~12% increase enought to jump over the gap with Intel. BTW, in some cases 4MB of cache per a thread (8c Interlagos) might be very helpfull.
JF-AMD confirms (yet again...) that higher single thread performance (than 10h) generation comes from core level changes(IPC) and that new Turbo comes on top of that: http://www.amdzone.com/phpbb3/viewtopic ... 38#p193838
Of course, it should be higher. Nobody argues this. Even AMD publicly stated "up to 50% more int performance with 33% more cores". The questions which are left are a) how much of it comes from much bigger cache and how much from architecture tuning and b) Is that ~12% increase enought to jump over the gap with Intel. BTW, in some cases 4MB of cache per a thread (8c Interlagos) might be very helpfull.
You can read,can you? Read slowly and carefully :
Quote:
All of the single thread advantages are without turbo mode. Turbo only makes it better.
AMD made a comment about BD throughput performance across variety of server workloads(which are mostly multithreaded),when all the cores in BD and Magny Cours work full steam most of the time. This is the average from those workloads.Saying that it has 12.5% IPC advantage over MC just from "50% faster with 33% cores" is not correct. Westemere has 50% more cores and is around 33% faster in server workloads than similarly clocked Nehalem (TurboBoost is not the same on these two).This shows you that even with workloads that should scale well with more cores you need uarchitecture improvements in order to get much better results than core count increase indicates you will get otherwise(with no such improvements).
Paul DeMone wrote:
Have you and/or AMD ever stated that single thread IPC would be higher?
Maybe if you bothered to read you will know the answer to your question.
Without sharing in mutithreaded workloads,a single core actually has everything on its disposal,going from massively better front end (vs fam10h) to massively better FP unit,effectively wider integer cores that have 2x L/S BW(2 128bit load and 1 128bit store per clock,full OoO load/store capability) to large inclusive 2MB L2 cache and 8MB of L3 cache that works ~20% faster now(2.4+Ghz in BD).On top of that you have 30% faster IMC due to design changes and 20% higher clocked DRAM support. New aggressive prefetchers and much improved branch prediction should also be mentioned.
Yeah "single thread IPC" will surely be lower. /sarcasm
JF-AMD confirms (yet again...) that higher single thread performance (than 10h) generation comes from core level changes(IPC) and that new Turbo comes on top of that: http://www.amdzone.com/phpbb3/viewtopic ... 38#p193838
Of course, it should be higher. Nobody argues this. Even AMD publicly stated "up to 50% more int performance with 33% more cores". The questions which are left are a) how much of it comes from much bigger cache and how much from architecture tuning and b) Is that ~12% increase enought to jump over the gap with Intel. BTW, in some cases 4MB of cache per a thread (8c Interlagos) might be very helpfull.
First, why does it matter where the performance increases come from? I am not sure what your agenda is, but I have never seen anyone dismiss performance because it came from one place or another. Since it is a brand new architecture and the old one is ~7 years old, I'll let the world draw their conclusions.
Actually, when you look at server performance (which is what all of the projections are based on), currently we are ~5% faster in integer and ~20% faster in floating point.
Knowing that we are going to be ~50% faster, sandy bridge has to be ~55% faster just to match performance. And I don't see that happening. 2 more cores is not going to buy them a 55% performance increase. As it was pointed out before, 50% more cores bought them a 33% performance increase. So what does 33% more cores buy them?
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