Aceshardware

hyc · Joined: 23 Sep 2007 Posts: 60 Location: Los Angeles, CA

So far, I see much better performance with existing Opteron servers than with comparably priced Niagara servers. You can't get around Amdahl's law here; allowing single-thread performance to lag while you aim for massive numbers of threads is a losing proposition.

TacoBell · Joined: 17 Aug 2007 Posts: 263

I wonder how much of AMD's price reflects the chance of a significant outcome of the various lawsuits that are pending against Intel.

Paul DeMone · Joined: 29 Aug 2007 Posts: 455 Location: Great white north

hyc wrote:

So far, I see much better performance with existing Opteron servers than with comparably priced Niagara servers. You can't get around Amdahl's law here; allowing single-thread performance to lag while you aim for massive numbers of threads is a losing proposition.

Well as unlikely as it seems apparently a small segment of server
buyers do find Niagara boxes useful and are willing to pay the
ludicrous price Sun charges for them. Do you not think that an
x86 analog of Niagara would have a somewhat larger potential
customer base than the one Sun is currently servicing?

Paul DeMone · Joined: 29 Aug 2007 Posts: 455 Location: Great white north

Wouter Tinus wrote:

Quote:

Perhaps AMD could bring to market a highly threaded, highly CMP
in-order x86 server chip along the lines of Sun's Niagara series. It
is niche but a niche Intel is unlikely to follow AMD into.

This idea sounds an awful lot like Larrabee:

Only superficially. Larrabee will be oriented to very FP intensive,
high bandwidth per thread workloads with relatively predictable
memory access patterns and branches. Niagara is very weak in
FP and is highly oriented to low ILP, high MLP commercial type
workloads, i.e. light on FP, very heavy on low data intensity
integer computation with many small hard to predict memory
accesses and branches.

sega.amx · Joined: 22 Jul 2007 Posts: 8

Paul DeMone wrote:

Perhaps AMD could bring to market a highly threaded, highly CMP
in-order x86 server chip along the lines of Sun's Niagara series. It
is niche but a niche Intel is unlikely to follow AMD into. For volume
maybe AMD could use a cost and power reduced variant of Griffin
to find a market seam between Atom and low end C2Ds in terms
of power, performance, and cost.

not as long as OEM's will rule AMD and tell them what they want.

jack · Joined: 27 Jun 2007 Posts: 330

jack wrote:

By the way, what happened to dual core K10s? There were supposed to arrive in Q2 2008, but there have been very little information about them recently.

Maybe AMD realized that dual core K10 wouldn't be any faster than dual core K8 and decided to skip altogether dual core K10 parts for 65nm?

HKEPC is now reporting that dual core 65nm K10s are cancelled (Kuma and Phenom FX):
http://www.google.com/translate?u=http%3A%2F%2Fwww.hkepc.com%2F%3Fid%3D1290%26fs%3Dc1h&hl=en&ie=UTF8&sl=zh-CN&tl=en

inf64 · Joined: 04 Sep 2007 Posts: 68

jack wrote:

By the way, what happened to dual core K10s? There were supposed to arrive in Q2 2008, but there have been very little information about them recently.

Maybe AMD realized that dual core K10 wouldn't be any faster than dual core K8 and decided to skip altogether dual core K10 parts for 65nm?

HKEPC is now reporting that dual core 65nm K10s are cancelled (Kuma and Phenom FX):
http://www.google.com/translate?u=http%3A%2F%2Fwww.hkepc.com%2F%3Fid%3D1290%26fs%3Dc1h&hl=en&ie=UTF8&sl=zh-CN&tl=en

So what,with their focus on 45nm Shanghai,there is no point releasing DC or FX parts on 65nm.We'll have 9950 @2.6Ghz and that's it.
Come Q3(Octobar) and you'll have 2.6-2.8Ghz 45nm 95W Deneb/Deneb FX chips in QC and possible Tri Core forms.3 cores(1 core disabled) done at 45nm without the large L3 cache will be faster,lower power draw/TDP and cheaper than Dual Core K10s made @ 65nm.No brainer for AMD.
In the meantime they've just released the 3Ghz 76W dual core Brisbanes for Business Class and 3 cores QC for Business/Client.
Opteron 8 and 2 series reached 2.5Ghz.Not all news is bad as you can see.

jack · Joined: 27 Jun 2007 Posts: 330

45nm K10s without L3 cache will definitely not be available in 2008.

The problem for AMD is that they will not have a decent (= good performance without a large die size) mainstream CPU for another year. ~240mm^2 Shanghai will not help here.

inf64 · Joined: 04 Sep 2007 Posts: 68

L3 cacheless quad core is on the way in late 2008,with its ~180mm2 die size,it fits in mainstream performance segment and is a lot smaller than either 65nm K10 or 45nm K10(with L3).It will draw less power,cost less and OC probably better than Deneb with L3.Yes it will probably be somewhat slower,but that's up to reviews to find out.

jack · Joined: 27 Jun 2007 Posts: 330

inf64 wrote:

L3 cacheless quad core is on the way in late 2008,with its ~180mm2 die size,it fits in mainstream performance segment and is a lot smaller than either 65nm K10 or 45nm K10(with L3).It will draw less power,cost less and OC probably better than Deneb with L3.Yes it will probably be somewhat slower,but that's up to reviews to find out.

Can you give some sources which say that cacheless QC parts will be available in 2008?

It's very hard to believe, since tape-out of Shanghai occured just in the begining of this year, thus parts with L3 cache should be available in late 2008. It would be logical to assume at cacheless parts would arrive 1-2 quarters later.

Paul DeMone · Joined: 29 Aug 2007 Posts: 455 Location: Great white north

jack wrote:

inf64 wrote:

L3 cacheless quad core is on the way in late 2008,with its ~180mm2 die size,it fits in mainstream performance segment and is a lot smaller than either 65nm K10 or 45nm K10(with L3).It will draw less power,cost less and OC probably better than Deneb with L3.Yes it will probably be somewhat slower,but that's up to reviews to find out.

Can you give some sources which say that cacheless QC parts will be available in 2008?

It's very hard to believe, since tape-out of Shanghai occured just in the begining of this year, thus parts with L3 cache should be available in late 2008. It would be logical to assume at cacheless parts would arrive 1-2 quarters later.

What? You don't think AMD will dedicate a portion of the first few quarter
of production of its slowly ramping and likely defectivity challenged 45
nm wafer production for dual core desktop processors? What could
possibly generate more revenue per wafer than price bombing L3-less
45 nm K8L dual cores against faster low end Conroe desktop SKUs as
Intel winds down x86 production in 65 nm? ;^)