Aceshardware

up · Joined: 06 Oct 2007 Posts: 36

AMD Ships 45-Nano Shanghai, Deneb Chips
http://www.informationweek.com/news/showArticle.jhtml?articleID=206901459

Alberto · Joined: 04 Sep 2007 Posts: 111 Location: Italy

inf64 wrote:

EaS wrote:

May seem so, but the cache sizes are confirmed here (and 1.648 V?)

Today officials (AMD) said that 45nm chips would consume 15% less energy(even tho they feature 3x more L3 cache,so it's not a straight die shrink from 65nm) than 65nm parts,i presume per same clock.This explains the HKEPC slide claiming TDP drop from 125 to 95W for top speed bins(65nm-> 45nm).

This result is under the expectations (20%) even with two times the cache on die. We'll see the other news in this cpu, for example a full speed L3 can give more watts to the power budget, a better IMC can be hotter....who knows. What matters is the performance, we'll see.
One thing is sure, Shanghai and Nehalem are BIG chips for a large consumer production, IMO a die size of 250/260 mm2 is not the right solution for a good profit. Both companies need of a strategic rethink.

Alberto.

inf64 · Joined: 04 Sep 2007 Posts: 68

Alberto,Shanghai won't be in 250mm2 range..It will be around 146-160mm2 and a lot smaller than Nehalem Quad Core part.

Gabriele Svelto · Joined: 27 Jun 2007 Posts: 274 Location: Milano, Italy

Alberto wrote:

One thing is sure, Shanghai and Nehalem are BIG chips for a large consumer production, IMO a die size of 250/260 mm2 is not the right solution for a good profit. Both companies need of a strategic rethink.

Both companies will keep their dual-core offerings and IMHO that will still make most of the volumes. Dual-cores already provide very little benefit to end users, quad-cores are simply worthless unless, especially so in laptop offerings where they have the burden of a larger power envelope.

The_Wolf_Who_Cried_Boy · Joined: 30 Sep 2007 Posts: 19

Paul DeMone wrote:

Carfax wrote:

Does anyone know what we can expect from Shanghai performance wise? Will it address whatever issues were plaguing Barcelona?

Barcelona was a huge letdown for me. I wanted to go back to AMD, but the performance just wasn't there.. :(

What the hell happened with Barcelona anyhow? It's barely faster than the K8!

I wouldn't expect much of a frequency boost from AMD's 45 nm process
however this will be AMD's second crack at this microarchitecture so they
should be able to squeeze critical paths based on their experience with
the original 65 nm version. AMD should be able to ship quad server
parts at 2.6 GHz in 45 nm, maybe 2.8 GHz if they push really hard.

Not that I particularly know what I'm talking about but isn't a design's layout optimised for the process node which the product will spend most of it's life on, that being 45nm for the K10H (or whatever people want to call it)? Considering the original 65nm design was expected to reach 2.8GHz under a 95 watt TDP and is obviously suffering some serious speed issues do you really hold such little hope for competative clocks?

Alberto · Joined: 04 Sep 2007 Posts: 111 Location: Italy

inf64 wrote:

Alberto,Shanghai won't be in 250mm2 range..It will be around 146-160mm2 and a lot smaller than Nehalem Quad Core part.

You mean 270 mm2 range ;-)
You are wrong, look at the die photo. Shanghai is around a 18.8X14.2 mm2 cpu if you make a calculation on the core die size: old core around 25.5 mm2, new 45nm core 25.5X0.7= 17.8 mm2. About sram cells, they are pretty big aka around 11.5-12 mm2/ MB, i don't know the reason, maybe to lower the leakage.
Your figure is for a L3 free quad core cpu, but it sounds like an useless AMD celeron. Moreover Intel can ship a Nehalem without L3, so where is the problem?

Alberto.

Alberto · Joined: 04 Sep 2007 Posts: 111 Location: Italy

inf64 wrote:

Alberto,Shanghai won't be in 250mm2 range..It will be around 146-160mm2 and a lot smaller than Nehalem Quad Core part.

Now there is the confirmation, with a nice wafer photo:

http://www.theinquirer.net/gb/inquirer/news/2008/03/05/amd-shows-45nm

a little less than 21 cpus in vertical, a little less than 16 cpus in orizontal
or a little less than 336 dies on a 300X300= 90000 mm2 area:
Shanghai is a 260/270 mm2 cpu.

Alberto

EaS · Joined: 09 Sep 2007 Posts: 8

inf64 wrote:

CPU-z can't read Vcore correctly with Shanghai.
Today officials (AMD) said that 45nm chips would consume 15% less energy(even tho they feature 3x more L3 cache,so it's not a straight die shrink from 65nm) than 65nm parts,i presume per same clock.This explains the HKEPC slide claiming TDP drop from 125 to 95W for top speed bins(65nm-> 45nm).

You're right, this seems more like it:

up · Joined: 06 Oct 2007 Posts: 36

Paul DeMone wrote:

jokerman wrote:

I'm embarrased that by my own die counting, I'm coming up with a die size similar to Tukwila ...

I suspect you are off by about a factor of four.

BTW... speaking about factor of four?
Hey... what abut this?
Sweet Little Sixteen! :lol:

http://www.pcgameshardware.de/aid,634840/News/Cebit_2008_AMD_zeigt_System_mit_16_Kernen_in_45_Nanometer/

Paul DeMone · Joined: 29 Aug 2007 Posts: 455 Location: Great white north

up wrote:

Paul DeMone wrote:

jokerman wrote:

I'm embarrased that by my own die counting, I'm coming up with a die size similar to Tukwila ...

I suspect you are off by about a factor of four.

BTW... speaking about factor of four?
Hey... what abut this?

Well... I guess there are people in the world who can't afford a real server. :-P

martinw · Joined: 06 Sep 2007 Posts: 116

Paul DeMone wrote:

Well... I guess there are people in the world who can't afford a real server. :-P

:-)

Hans de Vries · Joined: 07 Aug 2007 Posts: 85

Time for an update with Shanghai pictures and a Nehalem picture not so obscured by wiring.

Regards, Hans

Michael Westman · Joined: 27 Jun 2007 Posts: 24 Location: Amsterdam

Hans de Vries wrote:

Time for an update with Shanghai pictures and a Nehalem picture not so obscured by wiring.

Regards, Hans

Excellent work Hans! What strikes me is the L3 cache density. Why is the AMD L3 cache about the same as L2? It's not like it's very fast, if you think of Barcelona...?

Gabriele Svelto · Joined: 27 Jun 2007 Posts: 274 Location: Milano, Italy

Michael Westman wrote:

Excellent work Hans! What strikes me is the L3 cache density. Why is the AMD L3 cache about the same as L2? It's not like it's very fast, if you think of Barcelona...?

I seem to remember that they basically reused the cells designed for the L2 and yeah, it's not very fast.

rcf · Joined: 02 Oct 2007 Posts: 33

Quick question:

If i have one of the few AM2 motherboards that supports Phenom, will it be compatible with Shanghai?