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idontcare
Joined: 10 Mar 2008
Posts: 22
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 Posted: Sat Jun 07, 2008 9:35 pm Post subject: |
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| JumpingJack wrote: | AMD issued statements to a couple of reviewers that Brisbane did indeed lose two cycles -- AMD explained it as 'reserved the capability for increasing cache if needed' -- which, in my opinion, was a dodge.
Jack |
What do you propose AMD was dodging?
I am told by folks who would know such things that this was in fact the decision at time-zero in the design.
We could certainly argue amongst ourselves the relative merits of AMD making such a decision, but we need not really invoke images of anything more sinister at play than just management making trade-offs to hedge against an uncertain future at 65nm.
It wouldn't be the first time AMD allowed for plans of high(er) cache models only to never tape them out (Mustang anyone). |
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EduardoS
Joined: 22 Mar 2008
Posts: 98
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JumpingJack
Joined: 05 Oct 2007
Posts: 115
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| Posted: Sun Jun 08, 2008 5:09 am Post subject: |
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Thanks, I will read the article in detail.... did not notice if they did a Windsor to compare, but will look at it in detail.
Also, http://products.amd.com/en-us/NotebookCPUSideBySide.aspx?id=432&id=434&id=435
I did not find a 2 Meg L2 (2x1) in AMD's product list, they only list 1 Meg (512x2) ultras. Do you have a different link from AMD showing otherwise?
Jack
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JumpingJack
Joined: 05 Oct 2007
Posts: 115
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| Posted: Sun Jun 08, 2008 5:16 am Post subject: |
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| idontcare wrote: |
What do you propose AMD was dodging?
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That their process tech was weaker than expected. But it could actually be true... I am just speculating, based on the info when Brisbane launched, the move to put 2 xtra metal layers into Barcelona, and the focus (advertisement at IEDM) for ultra-low K as the next key enabler in their 45 nm process. |
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EduardoS
Joined: 22 Mar 2008
Posts: 98
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JumpingJack
Joined: 05 Oct 2007
Posts: 115
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| Posted: Sun Jun 08, 2008 6:03 am Post subject: |
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Interesting, one spec sheet shows 2x1, another shows 1 total ... I believe yours instead of the search engine.
jack
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Blitzkrieg
Joined: 31 Jul 2007
Posts: 64
Location: New Zealand
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| Posted: Sun Jun 08, 2008 12:13 pm Post subject: |
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For the Turion Ultra, there were 3 models released afaik and the top model had 2x1meg cache the other 2 were 512k.
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who?
Joined: 01 Sep 2007
Posts: 528
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| Posted: Sun Jun 08, 2008 2:44 pm Post subject: |
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Bottom line, there is no issue to do a fast L3 cache.
who?
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Johan
Joined: 23 Jul 2007
Posts: 141
Location: Belgium
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| Posted: Sun Jun 08, 2008 3:49 pm Post subject: |
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| who? wrote: | Bottom line, there is no issue to do a fast L3 cache.
who? |
Disagree. When you got to power 4 cores in a power envelop of about 80W, it seems that Power consumption is a serious issue. It seems that AMD traded in a tiny bit of performance for a large reduction in power consumption.
The small L2-cache has more impact than the slow L3...I know I am stating the obvious, but I don't see why many people are so focused on the relatively high latency of the L3. Tulsa's L3 was >100 cycles and it did pretty well compared to it's predecessor. |
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EduardoS
Joined: 22 Mar 2008
Posts: 98
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| Posted: Sun Jun 08, 2008 4:22 pm Post subject: |
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| Blitzkrieg wrote: | | For the Turion Ultra, there were 3 models released afaik and the top model had 2x1meg cache the other 2 were 512k. |
Every Turion Ultra has 2x1MB, the recently launched Turion X2 RM-70 has just 2x512kb. |
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savantu
Joined: 21 Mar 2008
Posts: 25
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| Posted: Sun Jun 08, 2008 5:42 pm Post subject: |
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| who? wrote: | Bottom line, there is no issue to do a fast L3 cache.
who? |
Nor is Nehalem's.
At 39 cycles , it is slow. |
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who?
Joined: 01 Sep 2007
Posts: 528
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| Posted: Mon Jun 09, 2008 1:03 am Post subject: |
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| savantu wrote: | | who? wrote: | Bottom line, there is no issue to do a fast L3 cache.
who? |
Nor is Nehalem's.
At 39 cycles , it is slow. |
Try to do by yourself 8Megs at 39cycles and call me back :) Those are not running at low frequency. Did you ever participate to any CPU design? I think you are forgetting that those CPUs are the most complex machine build by humans a little bit too easily. It is faster than other L3 on the market yet!
who? |
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inf64
Joined: 04 Sep 2007
Posts: 69
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| Posted: Mon Jun 09, 2008 1:59 am Post subject: |
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Can anyone(Johan maybe) in short summarize all relevant L3 numbers for K10 and Nehalem ?
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mas
Joined: 31 Jul 2007
Posts: 75
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| Posted: Mon Jun 09, 2008 2:25 am Post subject: |
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| who? wrote: | | savantu wrote: | | who? wrote: | Bottom line, there is no issue to do a fast L3 cache.
who? |
Nor is Nehalem's.
At 39 cycles , it is slow. |
Try to do by yourself 8Megs at 39cycles and call me back :) Those are not running at low frequency. Did you ever participate to any CPU design? I think you are forgetting that those CPUs are the most complex machine build by humans a little bit too easily. It is faster than other L3 on the market yet!
who? |
Itanium's 12MB L3 is 14 cycles. |
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LiamC
Joined: 23 Jul 2007
Posts: 76
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| Posted: Mon Jun 09, 2008 8:44 am Post subject: |
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At what frequency (and what is the maximum frequency is it likely to hit)?
Convert those cycle numbers to ns. Which is faster?
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