Aceshardware

EduardoS · Joined: 22 Mar 2008 Posts: 110

Alberto wrote:

So the LARGE Tulsa cache is not so bad, without power concerns and at full speed would have a latency of around 15ns. Yet IPF looks better ;-).

Thanks.

Alberto.

Not exactly, when raising the L3 frequency it's latency in L3 cycles also increase and in ns remains almost the same.
Higher frequencies in caches doesn't mean lower latencies.

Alberto · Joined: 04 Sep 2007 Posts: 111 Location: Italy

EduardoS wrote:

Alberto wrote:

So the LARGE Tulsa cache is not so bad, without power concerns and at full speed would have a latency of around 15ns. Yet IPF looks better ;-).

Thanks.

Alberto.

Not exactly, when raising the L3 frequency it's latency in L3 cycles also increase and in ns remains almost the same.
Higher frequencies in caches doesn't mean lower latencies.

So we cannot expect much from the new Shanghai L3 even if at full core speed, moreover it will be 3 times larger....an issue for having better latencies. This is one correct interpretation ?

Alberto.

EduardoS · Joined: 22 Mar 2008 Posts: 110

Alberto wrote:

So we cannot expect much from the new Shanghai L3 even if at full core speed, moreover it will be 3 times larger....an issue for having better latencies. This is one correct interpretation ?

Alberto.

Yes, you got the point ;)

Opteron · Joined: 16 Mar 2008 Posts: 55

jamannetje wrote:

I wonder if it is possible to deactivate the L3-cache and benchmark that. At the moment I too think that the L3-cache is partly to blame.

Any news on this ? I would be also interested in a L3-less K10 test :)

cheers

Opteron

alavo03 · Joined: 23 Mar 2008 Posts: 16 Location: Tarragona, Spain

Speaking of Intel Tulsa, it was a very good design with slow and inefficient processors. The L3 latency in Netburst cores always had been terrible. Remember Northwood Extreme Edition (2 MB L3).

One of the main reasons was the superpipelined architecture and the Replay System that forced the latency of the L2 cache and L3 to be dependant of the replay loop/loops pipeline depht.

.

Anyone can shed more light on Intel Tejas affair? I mean microarchitectural details.

Two excellent articles about Replay System:
http://www.xbitlabs.com/articles/cpu/print/replay.html
http://www.xbitlabs.com/articles/cpu/print/netburst-2.html

Xeon Tulsa slides:
http://www.hotchips.org/archives/hc18/3_Tues/HC18.S9/HC18.S9T1.pdf

Regards, Carlos