Aceshardware

Uffe Merrild · Joined: 27 Jun 2007 Posts: 108 Location: Silkeborg, Denmark

Michael Westman wrote:

Blitzkrieg wrote:

I am an amd fan, but basically you just straight out have to admit, it is disaster.
How can it have so many improvements and really not seem that much faster than K8.

I agree, this is a disaster. Relatively small improvements compared to K8, initial low clock-speed, high power consumption. FFS AMD, you have had 4 years since the initial A64 release and this is the best you can come up with?

I haven't had an Intel processor since Pentium 233 mmx, but I can assure you I'll have a Penryn based cpu in a couple of months. :)

I'll second that comment.

Today I have a C2D E6600 so I won't change anything. The thing runs my games like a charm, no reason to up the frequency or performance at all :)

I was an AMD fan too - but this is like returning to the initial C2D days, but even worse since we now know that AMD won't have anything competitive around for a very long time. I hope some fools keep buying their CPUs so they will stay in business until their next CPU. Maybe that will turn out better.

Too bad AMD can't buy the Alpha design team another time to make a new world-class processor like they did with the K7 ;)

inf64 · Joined: 04 Sep 2007 Posts: 69

Alberto,i can't upload the pdf for you here,but look up the one named AMD_ACP_WPv7.pdf on the google.
AMD list the "Power for memory controller (% of ACP)" :

16% for 105W ACP (120W TDP)
20% for 75W ACP(95W TDP)
23% for 55W ACP(68W TDP)

This translates to roughly 15W for IMC in all of the above cases(AMD list this as just IMC,but it is also 2 DCTs,SRQ and CB switch)

jack · Joined: 27 Jun 2007 Posts: 359

inf64 wrote:

jack wrote:

inf64 wrote:

PS I just looked at pcper article and the power consumtion(even on the OCed 2.6Ghz,1.3V part) is really good.Phenom shines @idle and it's good @ load.At least one positive :)

PCPer article shows 2.6GHz Phenom having a higher power consumption under load than 3GHz Core2 Quad. I wouldn't call that "good".

Anandtech has power consumption numbers made with identical video cards and they show that Phenom has a higher power consumption than identically clocked 65nm Core2 Quad.

Yes,but C2Q doesn't have integrated NB with 2DCTs,IMC,CB Switch and SRQ ,does it?Add in 15% on top of C2Qs numbers and you get a more realistic picture.
Of course i am talking about CPU only power cons. ,not system level.

PCper article that you quoted has only system power consumption numbers.

Alberto · Joined: 04 Sep 2007 Posts: 111 Location: Italy

inf64 wrote:

Alberto,i can't upload the pdf for you here,but look up the one named AMD_ACP_WPv7.pdf on the google.
AMD list the "Power for memory controller (% of ACP)" :

16% for 105W ACP (120W TDP)
20% for 75W ACP(95W TDP)
23% for 55W ACP(68W TDP)

This translates to roughly 15W for IMC in all of the above cases(AMD list this as just IMC,but it is also 2 DCTs,SRQ and CB switch)

Sorry, i cannot find the paper :-(.
Yet 16% for 105W ACP means 14% for 120W TDP, very good! some hard numbers from Amd. Maybe this the reason why Intel has raised the TDP figure of Nehalem up to 90/130W instead of the traditional 80/120W values of actual Xeons.

Thanks.

Alberto.

inf64 · Joined: 04 Sep 2007 Posts: 69

Alberto wrote:

inf64 wrote:

Alberto,i can't upload the pdf for you here,but look up the one named AMD_ACP_WPv7.pdf on the google.
AMD list the "Power for memory controller (% of ACP)" :

16% for 105W ACP (120W TDP)
20% for 75W ACP(95W TDP)
23% for 55W ACP(68W TDP)

This translates to roughly 15W for IMC in all of the above cases(AMD list this as just IMC,but it is also 2 DCTs,SRQ and CB switch)

Sorry, i cannot find the paper :-(.
Yet 16% for 105W ACP means 14% for 120W TDP, very good! some hard numbers from Amd. Maybe this the reason why Intel has raised the TDP figure of Nehalem up to 90/130W instead of the traditional 80/120W values of actual Xeons.

Thanks.

Alberto.

No problem :).Anyway ,i managed to upload the file to rapidshare :)
http://rapidshare.com/files/70915760/AMD_ACP_WPv7.rar.html
I guess intel's numbers for Nehalem could be similar ,hence they upped the TDP to 90/130W.

K10's Northbridge uses a bit more power in AM2 boards since the uni plane pwm brings in higher Vddnb-and this is the reason the NB clock in socketF uni plane boards is 200Mhz slower.
The sckF+/AM2+ boards supply lower vddnb and hence the higher clock for NB part(with the same power consumption).
But all this "lower than cores freq." stuff is much clearer in recent news of L3 problem(or hot spot problem) in NB.

Blitzkrieg · Joined: 31 Jul 2007 Posts: 64 Location: New Zealand

I think they would have been just better off trying to to just improve the cache and mem system further(prolly double the L2 at least) and just optimise K8 for 65nm.
Not going monolithic and adding an extra HT link would have been probably needed as well.
Its interesting the latest 65nm G2 K8s, they put cache latency back to what it was, adds a suprising amount of speed at the 3-3.2ghz range.

As it is, I think they should just go for dual core and use dual dies. Stuff this monolithic chest beating rubbish.

no@spam.com · Joined: 07 Oct 2007 Posts: 69

> I think they would have been just better off trying to to just improve the
> cache and mem system further(prolly double the L2 at least) and just
> optimise K8 for 65nm.

AMD didn't see a need for a 2x1M Opteron in 65nm.
Which would have been okay if Barcelona had been on time.
By the time they realized Barcelona was late, it was too late to change plans.

> Not going monolithic and adding an extra HT link would have been
> probably needed as well.

The extra link will enable useful/fast 8-socket systems.
And it will, together with unganging, increase cross-fire bandwidth.

> Its interesting the latest 65nm G2 K8s, they put cache latency back to
> what it was, adds a suprising amount of speed at the 3-3.2ghz range.

G2 tops out at 2.7 GHz.
(Nor does it have 2x1M.)

Yeah, overall... coulda shoulda woulda. (Or however you spell that. :-)

jamannetje · Posted: Tue Nov 20, 2007 8:56 am Post subject:

Uffe Merrild wrote:

Minimum framerate is a bad benchmark if not done right. If you merely take the absolute minimum frame rate which the computer cranked out you won't get a fair picture. A hd read or similar interrupt will put any test of minimum frame rate buttoming out the scale if on an appropriate moment.

I agree, but the mean also doesn't say much about playability. Maybe a graph is still best to give a good view on that, another option would be a % of frames below a certain required minimum.

I still find it interesting to see a higher minimal framerate for AMD [b]in all benchmarks[i] than for Intel. (At this frequency)

Jeschael

Michael Westman · Joined: 27 Jun 2007 Posts: 24 Location: Amsterdam

Gabriele Svelto wrote:

Johan wrote:

Hmmm the extra 20 ns isn't that just a result of the fact that the CPU has to search through the L3 before it goes to the RAM?

I think we've already talked about this in another thread though I don't remember if it was here or on RWT. Anyway checking the L3 tags cannot take 20ns, that would be 40 cycles @ 2.0 GHz, that's extremely unlikely. Naturally if the L3 is cache controller is buggy/flawed and it needs an ugly fix to function properly it might become quite possible :)

According to tech-report the L3 cache latency is ~ 23ns when the northbridge is running at 1.8GHz (CPU @ 2.0Ghz) and ~19ns when the NB is running at 2.0GHz (CPU @ 2.5Ghz).

http://techreport.com/articles.x/13176/3

That would be the load to use latency IIRC.

Tech ARP says the latency in cycles should be less then 38 cycles.

http://www.techarp.com/showarticle.aspx?artno=424&pgno=2

http://www.techreport.com/articles.x/13633/4

In the phenom review with the NB running at 2.0GHz the L3 latency seem to be ~22ns. http://www.techreport.com/articles.x/13633/4

up · Joined: 06 Oct 2007 Posts: 38

Is this maybe more kind of squaring the circle?
Integration of L3/NB?
Simply to complicated?

Pjotr · Joined: 06 Aug 2007 Posts: 159

Uffe Merrild wrote:

Too bad AMD can't buy the Alpha design team another time to make a new world-class processor like they did with the K7 ;)

Perhaps AMD can buy the Itanium team? ;-)

Michael Westman · Joined: 27 Jun 2007 Posts: 24 Location: Amsterdam

up wrote:

Is this maybe more kind of squaring the circle?
Integration of L3/NB?
Simply to complicated?

IIRC Charlie wrote about this issue at the Inq some time ago. I don't remember exactly what it was and I can't find the article right now, but apparently there where some scaling issues with the K8 mem controller and AMD decided to have the K10 mem controller not being locked to the CPU speed. Personally I find this a bit contradictory considering the fastest dual-core K8 runs at 3.2GHz @ 90nm...

I have no clue why the L3 cache would have to run at the same speed as the NB though. Maybe it has something to do with the fact that the L3 cache also acts as a write buffer to memory as hinted in the THG review? (Yeah, I know, it's Tom's but still......)

Gabriele Svelto · Joined: 27 Jun 2007 Posts: 290 Location: Milano, Italy

Michael Westman wrote:

According to tech-report the L3 cache latency is ~ 23ns when the northbridge is running at 1.8GHz (CPU @ 2.0Ghz) and ~19ns when the NB is running at 2.0GHz (CPU @ 2.5Ghz).

http://techreport.com/articles.x/13176/3

That would be the load to use latency IIRC.

Tech ARP says the latency in cycles should be less then 38 cycles.

http://www.techarp.com/showarticle.aspx?artno=424&pgno=2

http://www.techreport.com/articles.x/13633/4

In the phenom review with the NB running at 2.0GHz the L3 latency seem to be ~22ns. http://www.techreport.com/articles.x/13633/4

Yeah, that's why I said that it is not possible that the added memory latency comes from it. If the full load-to-use latency of the L3 cache is ~20ns then the time needed to check the tags (and thus initiate a memory request on a miss) should be a fraction of that. If theInq's article on a problem regarding TLB & L3 cache interaction is true it might just be possible that in order to fix it memory requests have to go through a longer delay before being issued.

That's all speculation on my part obviously but I think we're starting to have enough data points to understand why K10 is making such a poor showing (lack of high-cloked parts asides).

inf64 · Joined: 04 Sep 2007 Posts: 69

Gabriele Svelto wrote:

Michael Westman wrote:

According to tech-report the L3 cache latency is ~ 23ns when the northbridge is running at 1.8GHz (CPU @ 2.0Ghz) and ~19ns when the NB is running at 2.0GHz (CPU @ 2.5Ghz).

http://techreport.com/articles.x/13176/3

That would be the load to use latency IIRC.

Tech ARP says the latency in cycles should be less then 38 cycles.

http://www.techarp.com/showarticle.aspx?artno=424&pgno=2

http://www.techreport.com/articles.x/13633/4

In the phenom review with the NB running at 2.0GHz the L3 latency seem to be ~22ns. http://www.techreport.com/articles.x/13633/4

Yeah, that's why I said that it is not possible that the added memory latency comes from it. If the full load-to-use latency of the L3 cache is ~20ns then the time needed to check the tags (and thus initiate a memory request on a miss) should be a fraction of that. If theInq's article on a problem regarding TLB & L3 cache interaction is true it might just be possible that in order to fix it memory requests have to go through a longer delay before being issued.

That's all speculation on my part obviously but I think we're starting to have enough data points to understand why K10 is making such a poor showing (lack of high-cloked parts asides).

We can at least hope that future (fixed*) versions of Phenoms will have northbridge clocked at least at the cores frequencies and that all the issues with HT3 on 790FX boards and non working CnQ2 will be fixed too.

HighTech4US · Joined: 19 Aug 2007 Posts: 10

jack wrote:

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3153
Very sad situation for the AMD and the industry

Have the engineers, who charlie saw dancing in the isles, been fired yet?

If this was what they were dancing about they should be gone.