Rumor says, the "L3 TLB bug" took the phenom-crew by surprise in warsaw, so there was no time to do anything better instantly...

Considering the 125TDP for a low speed bin I would like to know what the 3ghz samples were chewing up.
I don't think it is just the nb problem.

I wonder how AMD managed to create that poor L3 cache. It's small, running at a low clockspeed and has a very high latency (even when measured in cycles).

For example:
It seems that 2.4GHz Phenom will have L3 cache running at 2GHz, thus the latency will be about 19ns (according to the Tech report).

Core2 has IIRC 12 cycle L2 latency, thus the overall latency for 2.4GHz Core2 is 12/2,4 = 5ns!

Basically Phenom's L3 cache is 50% smaller and it's latency is almost four times as high. No wonder the performance is poor.

Nice read about zram!
Interview by MS
http://www.lostcircuits.com/memory/zram/

AMD is not using ZRAM. Nobody has currently used ZRAM in a production design.

There are a couple of issues relating to the L3 cache.

1. Relatively high access latency
2. Clock and voltage domain crossings
3. Additional memory latency

I don't know why the L3 latency is so high. Fundamentally, they should be able to hit about the same cycle times as they did on the K8's L2 caches. The main issue is power consumption. For the L3 cache, you probably want it to be somewhat slower, but more power efficient. It could be that thermal problems forced them to slow it down...

Clock crossings - these always add latency, pretty nasty. It's just an unavoidable aspect of AMD's architecture. Probably the clock ratio between the cores and uncores is a non-integer, which means there is a variable delay in access, and returning data.

Lastly, adding an L3 cache adds to overall memory access. IIRC, the latency for AMD's hierarchy is something like 3 cycles, ~10 cycles and ~23 cycles. To access memory, Barcelona first has to check the tags in the L1 and L2 caches, then send a request which crosses a clock domain, check the L3 tag, and then if it misses, finally send to the memory controller. So however long it takes to check the L3 tags is all additional memory latency...

Of course to compensate, I think the L2 latency is lower, but I don't know how long it takes to determine a miss.

DK

fyi... Kingston DDR2 1066MHz (CL7-7-7-20 @ 1.8V)
http://stocks.us.reuters.com/stocks/article.asp?WTmodLOC=C3-News-1&symbol=AMD&docID=358-200711191108BIZWIRE_USPR_____BW5231-29D21S8VIJT7JF10F30H2O2FOO