Aceshardware

shank15217 · Joined: 09 Oct 2007 Posts: 17

The l3 cache is also supposed to provide some flexibility to cache sizes in the future. Current core 2 designs are providing a massive 12 mb l2 cache which is not helping amd's cause. On latency sensitive workloads phenoms would have benefited from a simpler faster cache design, a rare case where server optimization isn't bringing dividends on desktop workloads.

up · Joined: 06 Oct 2007 Posts: 38

Quote:

L3 Cache
To make up for the relatively small L2 cache, K10 acquired a shared between all cores 2MB L3 cache with associativity of 32. L3 cache is adaptive and exclusive: it stores all data evicted from L2 caches of all cores as well as the data shared by several cores. When the core issues a line read request, a special check is performed. If the line is only used by one core, it is removed from L3 freeing room for the line that is evicted from L2 cache of the requesting core. If the requested line is also used by another core, it remains in the cache. However, in order to accommodate the line evicted from L2 cache, another – older – line will be removed in this case.

http://www.xbitlabs.com/articles/cpu/display/amd-k10_8.html#sect4
Is all that waiting not a waste?
reminds me on superlong FPU-pipelines, that couln't keep pace...

Pjotr · Joined: 06 Aug 2007 Posts: 159

shank15217 wrote:

Current core 2 designs are providing a massive 12 mb l2 cache which is not helping amd's cause.

To avoid planting any confusion: 2 separate 6 MB L2s, one L2 per 2 cores.

We might see more variations of cache/core overlaps when both Intel and AMD moves beyond 4 cores.

redpriest · Joined: 30 Aug 2007 Posts: 58

L3 latency is 40 cycles. Which while a lot, is not as much as ~130-200 cycles to memory.

It isn't a detriment to performance.

Paul DeMone · Joined: 29 Aug 2007 Posts: 530 Location: Great white north

redpriest wrote:

L3 latency is 40 cycles. Which while a lot, is not as much as ~130-200 cycles to memory.

It isn't a detriment to performance.

In isolation no. But AMD is going from a dual core with 1 MB of L2 per
core to a quad core with 512 KB L2 per core plus a 1/4 share of a 2MB
L3 with 40 cycle latency. It is not that hard to see cases where that is
a step backwards.

lux_interior · Joined: 26 Jul 2007 Posts: 252

Not to mention that K10's L3 also seems to have much smaller bandwidth than its L2.

up · Joined: 06 Oct 2007 Posts: 38

Is this caused by the L3/NB Lock?
http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_15331_15332%5E15348,00.html

Desti · Joined: 09 Aug 2007 Posts: 38

up wrote:

Is this caused by the L3/NB Lock?
http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_15331_15332%5E15348,00.html

Yes, the 9500 and 9600 have 1800 MHz NB speed while the 9700 has 2000 MHz.

LiamC · Joined: 23 Jul 2007 Posts: 82

An update on ZRAM. This appeared in the latest article at LostCircuits

http://www.lostcircuits.com/advice/2007/

Page 3, ..."Innovative Silicon Inc, the inventor and manufacturer of capacitor-less DRAM or ZRAM finally admitted that the approach they were taking is not viable. Instead, ISI is moving on to the second generation of Z-RAM using biploar effects, rather than field-effect charge switching."...

j3pflynn · Joined: 28 Jul 2007 Posts: 18

LiamC,
It's still viable, though. Whether it ever pans out for AMD remains to be seen, but Gen2 is compatible.
...The Z-RAM is built in a PD SOI technology, and the Gen2 approach is compatible with either PD or fully depleted (FD) SOI. It requires no additional processing steps, and can be tuned to perform for speed or density, Okhonin said. It also has been demonstrated to work in the multi-gate finFET devices.

Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.) was ISI’s first licensee, with an announced goal of using it in a logic technology to form L3 cache on AMD’s microprocessors. AMD also took a license for the Gen2 technology...

http://www.semiconductor.net/article/CA6512566.html?nid=3351&rid=868738879

jack · Joined: 27 Jun 2007 Posts: 359

But it would take years in best case situation until products based on second generation ZRAM would be available.

jack · Joined: 27 Jun 2007 Posts: 359

HKEPC has more information about K10 schedule:
http://www.hkepc.com/?id=755&fs=news
http://www.hkepc.com/database/images/2008020112590949693587898.jpg
http://www.hkepc.com/database/images/2008020112591151452978954.jpg

B3 Phehoms have been pushed to Q2, 2.4GHz model to May-June and 2.6GHz model to Q3.

B2 2.1-2.3GHz tri-cores will be available in March and B3 tri-cores in May-June (including 2.4GHz model).

If this news is correct, then so far 2.6GHz Phenom X4 has been delayed by three quarters from Q4 2007 to Q3 2008.

jack · Joined: 27 Jun 2007 Posts: 359

Some more information: http://www.dailytech.com/article.aspx?newsid=11191

2.6GHz Phenom X4 9950 - 140W TDP
2.5GHz Phenom X4 9850 - 125W TDP

Tri-cores will have 95W TDP at 2.1GHz,2.3GHz and 2.4GHz speeds.

Groo · Joined: 22 Jul 2007 Posts: 178

jack wrote:

HKEPC has more information about K10 schedule:
http://www.hkepc.com/?id=755&fs=news
http://www.hkepc.com/database/images/2008020112590949693587898.jpg
http://www.hkepc.com/database/images/2008020112591151452978954.jpg

B3 Phehoms have been pushed to Q2, 2.4GHz model to May-June and 2.6GHz model to Q3.

B2 2.1-2.3GHz tri-cores will be available in March and B3 tri-cores in May-June (including 2.4GHz model).

If this news is correct, then so far 2.6GHz Phenom X4 has been delayed by three quarters from Q4 2007 to Q3 2008.

I would say it is incorrect. Ask me again in a week. :)

-Charlie

Phenom · Joined: 22 Mar 2008 Posts: 4

jack wrote:

If this news is correct, then so far 2.6GHz Phenom X4 has been delayed by three quarters from Q4 2007 to Q3 2008.

2.6 GHz Phenom, or Phenom X4 9900 was never announced for Q4 2K7. Model 9700 were announced for December 2007, but was dismissed completely on count of B3 rev.

So technically 2.6 GHz is right on time - Q2 2K8 ;)