Aceshardware

Performance estimates of Llano started to popup on I-net.

We see that Llano performance a bit worse than Athlon X4 640+Radeon 5550.
Retail prices on newegg.com:
Athlon X4 640 - 99$.
AMD Radeon 5550 -61$.

Even w/o Intel competition the retail price can't be more than 160$.
There is no Core i3-21xx on shelves yet, but based on the price of Core i5-2300 @ 185$ we might safely assume that retail prices of Core i3-21xx we'll be inside 120-160$.

I'm pretty sure that if prices of Core i3-21xx and Llano X4 are about the same most of ordinary users will follow Core i3 route and most of gamers too because Core i3-21xx can beat Athlon X4 645 badly and apparently even more Llano X4.
And that leads us to gloomy conslusion that retail prices of Llano X4 will hardly be higher than 100$.

Doing the conclusion about the margin i leave for you.

From the same source:


For the PCMark05 subtest I'm both too lazy and can't care less about this program, for Cinebench the scores of current processors are:
Core i7 2600K - 6.83
Phenom II X6 1100T - 5.89
Core i7 950 - 5.56

And by pixel counting Bulldozer will do... 10.9... Yeah... 60% faster then SandyBridge...

Now for 3DMark06, cpu test:
Core i7 2600K - 6608
Phenom II X6 1100T - 5986
Core i7 950 ~ 5400

Counting pixels again for Bulldozer gives... 8757... Now just 33% faster than SandyBridge...

I'm assuming this slide is true as long you assume the slide about Llano is true, you know, same source...

"pixel counting"? It's something new for me in cpu comparison procedures.

BTW, have you noticed the remark "Estimates and projections subject to change". And the slide is dated by December-2010 only (!?).

And, BTW, now we have the answer on the question which was asked about months ago: Who believes that Phenom X6 1100T is equal to Core i7-950. That's AMD itself.

As discussed in many forums, these slides might be faked. A "Cinibench" benchmark, i7-950 with 1156 pin package, "epic performance", "first and only native 8-core processor" and a questionable slide design are some points raising some doubt.

Well, I wouldn't be able to tell if they are faked or not. Interestingly,
JF (twice) said he couldn't either. The only thing really wrong is the
"i" in cinibench in the small print.

The rest is right or wrong depending on one's interpretation of the
context. The slide discusses the "Performance Desktop" segment.
So if that is the context then I don't see anything really wrong.

The Intel platform table doesn't mention the i7-950 explicitly, It just
mentions Core i7, and there are currently 4 different Core i7 processors
in this segment.

The 80%+ performance increase in Cinebench 11.5 fits well with the
official AMD line of ~80% performance increase in FP throughput.
So it's not so surprising that one of the authors of this document
says what he said about the slide...

Regards, Hans

source: http://www.worldhostingdays.com/downloa ... /hS2a1.pdf

I wouldn't put serious attention to "Cinibench". It's printed in very small font and if a girl had done misprinting (Does she really know what "Cinibench" means?) nobody have checked it.
There were many misprinting on AMD site. The last, most notable, was "32nm" for Zacate/Ontario.

"epic performance", "first and only native 8-core processor".
They don't look very extravagant praises after the words that we've heard from Rick Brgman concerning Zacate/Ontario.

questionable slide design.
It's serious. Blue-chips companies usually put a lot of efforts into corporate disign.
Girls use templates and in that case it's very difficult to insert remarks under footer. Destroying a corporate outlook can lead to person's dismissal.

In any case that's very interesting comment.

If somebody had missed the act #1 with Brazos vs. Core i5, AMD has just started the act #2 Llano@1.8 vs. SB@2.0.

This time around, AMD promotes that Llano is capable to handle concurrent mixed cpu and gpu workload much better than Intel.
As Godfrey Cheng, Director of Client Technology Unit at AMD, clearly states in his post: Exposing the phantom x86 bottleneck.
.
If it's really true i'm curious what the reasons lie behind that supremacy in that kind of scenario?
Is it due to L3-cacheless architecture is better suited to that scenario than the architecture w/ Last Level Cache?
Or Hyperthreading works like brakes here?
Or it just due to the fact that SB runs more gpu workload in cpu cores?
What ideas?

Heavy usage of GPU is polluting the L3 cache and making it useless for CPU side.

I think AMD's solution of not sharing the caches between CPU and GPU side was a good choice, as the access patterns of the cache are so different in CPU and GPU side and they will not cooperate nicely (unless parts of the cache can be staticly locked to be used by only either side)

The new intel graphics cores should finally support hardware vertex shaders, so it should not calculate much more on cpu side.
(unless it's doing things like tessellation on software on cpu side)

HyperThreading's effect is that when there are really 4 threads with lots of things to do, 4 cores are doing better than 2 bigger cores with HT, while when there is only 2 threads of work, 2 bigger cores are doing better.

I've already posted a possible explanation at Semiaccurate. I see a possible main reason in cache sharing and thus a resulting thrashing. It's not a matter of L3 or no L3, but more likely of:

• L2 size (Llano's cores should stress mem interface less due to 1MB L2 per thread vs. 128kB L2 per thread on SB)
• use of GPU's own caches (Radeon GPUs have several caches incl. some L2 cache - although I don't know about it's size in APU designs)
• no sharing of any caches between GPU and CPU, so only IMC is shared, which likely is optimized for certain request priorities

Edit: Oh noes! Heikki was faster since I didn't send this post immediately after writing it

Not heavy usage of GPU will also pollute L3.
I was pretty sure that Intel should have had it on its mind and bypass gpu traffic thru L3.

Speaking about HT in that case I meant that I don't exclude the special tuning was applied
for unefficient allocation of threads per cores. Who knows. At least we can't exclude this.

The scenarion was a bit of unrealistic too. It was very skewed into gpu side.
Three of four workloads were heavy gpu (video) bound. And even fith Flip 3D is gpu bound also.
Human being needs chameleon's eyes to watch movie, rendering and playing simulteneously.
Or if he is of the kind of this, he is better off with d.GPU. Is not it?

So my point is that cpu cores of Intel were much more loaded than that of AMD to treat the gpu.

Tesselation without DX11?



Is it so difficult to run a game with task manager open?

By the small improvement when going from 6 EU to 12 EU and overclocking I had the impression Sandy Bridgealways used CPU to improve graphics performance.

Or, rather, the IGP likely gets bandwidth-limited at some point.

Yeah, true, wich means it wastes a lot of bandwidth since 64-bits discrete GPUs performs better.

That was not the AMD's intention.

Nvidia Sees Increasing Demand Towards Standalone Mobile GPUs.
That's confirms those who need powerful graphics will go with d.GPU thus easily removing gpu bottleneck.