Aceshardware

Eric Bron · Joined: 31 Aug 2007 Posts: 134 Location: Switzerland

I've just noted a bunch of pdf already released here :

http://www.intel.com/pressroom/kits/events/idffall_2007/index.htm

jack · Joined: 27 Jun 2007 Posts: 359

Anandtech's article: http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3101

Most interesting thing is that there will be 8-core (16 threads 731M transistors) single die Nehalem! I didn't expect Intel to do that.

Dailytech has a die picture of Nehalem: http://images.dailytech.com/nimage/6015_large_I_AM_NEHALEM.jpg

It seems that cache per core is reduced (it looks that each core has 1.5MB of L2, unless Nehalem has also L3 cache).

Eric Bron · Joined: 31 Aug 2007 Posts: 134 Location: Switzerland

jack wrote:

Anandtech's article: http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3101

Most interesting thing is that there will be 8-core (16 threads 731M transistors) single die Nehalem! I didn't expect Intel to do that.

Dailytech has a die picture of Nehalem: http://images.dailytech.com/nimage/6015_large_I_AM_NEHALEM.jpg

It seems that cache per core is reduced (it looks that each core has 1.5MB of L2, unless Nehalem has also L3 cache).

now that's more exciting than day 0, where's Hans when we need him ?

Alberto · Joined: 04 Sep 2007 Posts: 111 Location: Italy

It seems to me the quad core part, look at the die photo. Moreover the transistor count is inconsistent with a octo core part with tweaked Merom/Penryn cores (better fpu unit?).

Alberto.

Alberto · Joined: 04 Sep 2007 Posts: 111 Location: Italy

Ha! an hidden article over INQ is saying that Hapertown is a "monster" over the new 1.6Ghz FSB chipset. The effective bandwidth is "doubled" thanks to a far better MC !!!.
The article will stay hidden for another hour or two from now.

Alberto.

jack · Joined: 27 Jun 2007 Posts: 359

Alberto wrote:

It seems to me the quad core part, look at the die photo. Moreover the transistor count is inconsistent with a octo core part with tweaked Merom/Penryn cores (better fpu unit?).

Alberto.

Yes, the picture is clearly a quad core part. Also 731M transistor count should be a transistor count of the quad core part. Maybe the 8-core part will be MCM? That would be more realistic on 45nm.

Hans de Vries · Joined: 07 Aug 2007 Posts: 89

jack wrote:

Anandtech's article: http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3101

Most interesting thing is that there will be 8-core (16 threads 731M transistors) single die Nehalem! I didn't expect Intel to do that.

Dailytech has a die picture of Nehalem: http://images.dailytech.com/nimage/6015_large_I_AM_NEHALEM.jpg

It seems that cache per core is reduced (it looks that each core has 1.5MB of L2, unless Nehalem has also L3 cache).

The image and the transistor count (713M) belongs to a four core
Nehalem. The L3 seems to be indeed the 8MB as was known but the
L2s seems to be larger as the 0.5MB previously mentioned. They
are more like 1MB. Could this have something to do with the rumor
of a later Shanghai version with 1MB L2s?

Regards, Hans

Paul DeMone · Joined: 29 Aug 2007 Posts: 530 Location: Great white north

Hans de Vries wrote:

The L3 seems to be indeed the 8MB as was known but the
L2s seems to be larger as the 0.5MB previously mentioned. They
are more like 1MB. Could this have something to do with the rumor
of a later Shanghai version with 1MB L2s?

Yeah I am sure when Intel heard this rumour they opened the Nehalem
design on a workstation, selected the L2 caches, opened a dialog box,
overwrote 512 with 1024, clicked on apply, and then closed the design.

Desti · Joined: 09 Aug 2007 Posts: 38

Desti · Joined: 09 Aug 2007 Posts: 38

Larger pic: http://planet64bit.de/node/2637

Hans de Vries · Joined: 07 Aug 2007 Posts: 89

Paul DeMone wrote:

Hans de Vries wrote:

The L3 seems to be indeed the 8MB as was known but the
L2s seems to be larger as the 0.5MB previously mentioned. They
are more like 1MB. Could this have something to do with the rumor
of a later Shanghai version with 1MB L2s?

Yeah I am sure when Intel heard this rumour they opened the Nehalem
design on a workstation, selected the L2 caches, opened a dialog box,
overwrote 512 with 1024, clicked on apply, and then closed the design.

You took the assumed cause-to-reaction the wrong way. We are talking
about a rumored end 2008/ early 2009 Shanghai follow up codenamed
Suzuka here....

Regards, Hans

Paul DeMone · Joined: 29 Aug 2007 Posts: 530 Location: Great white north

Hans de Vries wrote:

You took the assumed cause-to-reaction the wrong way. We are talking
about a rumored end 2008/ early 2009 Shanghai follow up codenamed
Suzuka here....

Ok, my mistake. I am not used to anyone at Ace's claiming Intel took
the initiative on something. ;-)