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 Post subject: Finally an image of Shanghai
PostPosted: Tue Mar 04, 2008 3:32 pm 
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Joined: Tue Sep 04, 2007 8:13 am
Posts: 111
Location: Italy
looks very interesting ! Now....Hans! we are waiting for your analysis ;-)

http://www.tomshardware.com/2008/03/04/ ... ocessors_/

Alberto.


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 Post subject: Re: Finally an image of Shanghai
PostPosted: Tue Mar 04, 2008 3:59 pm 
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Joined: Wed Jun 27, 2007 1:07 am
Posts: 26
Location: Amsterdam
Alberto wrote:
looks very interesting ! Now....Hans! we are waiting for your analysis ;-)

http://www.tomshardware.com/2008/03/04/ ... ocessors_/

Alberto.


It's very difficult to see anything in this picture except that the L2 cache is still 512 kB / core and the L3 cache is much larger than on Barcelona. By counting the L3 tags it seem to confirm a size of 6 MB...


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 Post subject:
PostPosted: Tue Mar 04, 2008 4:13 pm 
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Joined: Thu Aug 09, 2007 11:16 am
Posts: 38
http://www.amd.com/us-en/0,,3715_15503, ... dir=45nm01


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 Post subject: die size estimation ?
PostPosted: Tue Mar 04, 2008 5:44 pm 
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Joined: Wed Aug 22, 2007 9:24 am
Posts: 27
I'm embarrased that by my own die counting, I'm coming up with a die size similar to Tukwila ...

EDIT: maybe that's not a Shanghai wafer :oops:
EDIT2: Bingo, it's SRAM :/


Last edited by jokerman on Tue Mar 04, 2008 5:52 pm, edited 2 times in total.

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 Post subject: Re: die size estimation ?
PostPosted: Tue Mar 04, 2008 5:51 pm 
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Joined: Wed Aug 29, 2007 3:55 pm
Posts: 800
Location: Great white north
jokerman wrote:
I'm embarrased that by my own die counting, I'm coming up with a die size similar to Tukwila ...


I suspect you are off by about a factor of four.


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 Post subject: Re: Finally an image of Shanghai
PostPosted: Tue Mar 04, 2008 6:06 pm 
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Joined: Tue Sep 04, 2007 8:13 am
Posts: 111
Location: Italy
Michael Westman wrote:
Alberto wrote:
looks very interesting ! Now....Hans! we are waiting for your analysis ;-)

http://www.tomshardware.com/2008/03/04/ ... ocessors_/

Alberto.


It's very difficult to see anything in this picture except that the L2 cache is still 512 kB / core and the L3 cache is much larger than on Barcelona. By counting the L3 tags it seem to confirm a size of 6 MB...


Something is wrong. In Barcelona the single core is 6.5X a 256 KB L2 block +tags, in Shanghai only around 6X instead of the 9X figure with the reduction factors of 0.7 for logic and 0.5 for sram.
Shanghai cache seem larger than expected IMO, the whole chip seem too large. Looks like 260/270 mm2

Alberto.


Last edited by Alberto on Tue Mar 04, 2008 11:25 pm, edited 1 time in total.

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 Post subject:
PostPosted: Tue Mar 04, 2008 7:32 pm 
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Joined: Tue Aug 07, 2007 4:54 am
Posts: 40
Does anyone know what we can expect from Shanghai performance wise? Will it address whatever issues were plaguing Barcelona?

Barcelona was a huge letdown for me. I wanted to go back to AMD, but the performance just wasn't there.. :(

What the hell happened with Barcelona anyhow? It's barely faster than the K8!


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 Post subject:
PostPosted: Tue Mar 04, 2008 7:52 pm 
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Joined: Tue Sep 04, 2007 4:40 pm
Posts: 121
Carfax wrote:
Does anyone know what we can expect from Shanghai performance wise? Will it address whatever issues were plaguing Barcelona?

Barcelona was a huge letdown for me. I wanted to go back to AMD, but the performance just wasn't there.. :(

What the hell happened with Barcelona anyhow? It's barely faster than the K8!


Barely being 15-20% faster per clock than K8 on average and 40-50% in SSE intensive apps?
Barcelona is not a huge letdown,it was designed for servers primarily.It had its fare share of problems(TLB,low clocks) but soon this will be ironed out with B3 and 45nm transition.


Last edited by inf64 on Tue Mar 04, 2008 7:53 pm, edited 1 time in total.

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 Post subject:
PostPosted: Tue Mar 04, 2008 7:53 pm 
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Joined: Wed Aug 29, 2007 3:55 pm
Posts: 800
Location: Great white north
Carfax wrote:
Does anyone know what we can expect from Shanghai performance wise? Will it address whatever issues were plaguing Barcelona?

Barcelona was a huge letdown for me. I wanted to go back to AMD, but the performance just wasn't there.. :(

What the hell happened with Barcelona anyhow? It's barely faster than the K8!


I wouldn't expect much of a frequency boost from AMD's 45 nm process
however this will be AMD's second crack at this microarchitecture so they
should be able to squeeze critical paths based on their experience with
the original 65 nm version. AMD should be able to ship quad server
parts at 2.6 GHz in 45 nm, maybe 2.8 GHz if they push really hard.


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 Post subject:
PostPosted: Tue Mar 04, 2008 7:59 pm 
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Joined: Mon Jul 23, 2007 2:44 pm
Posts: 267
Location: Belgium
Carfax wrote:
Does anyone know what we can expect from Shanghai performance wise? Will it address whatever issues were plaguing Barcelona? Barcelona was a huge letdown for me. I wanted to go back to AMD, but the performance just wasn't there.. :(

What the hell happened with Barcelona anyhow? It's barely faster than the K8!


4 cores of Barcelona (2350) at 2.5 GHz are only beating a four core 3 GHz Opteron 2222
http://it.anandtech.com/IT/showdoc.aspx?i=3162&p=7

And here it is running circles around the same 4 cores at 3 GHz
http://it.anandtech.com/IT/showdoc.aspx?i=3162&p=8

A 2 GHz Barcelona (4 cores) is no less than 50% faster than 3.2 GHz Opteron (4 cores)
http://it.anandtech.com/IT/showdoc.aspx?i=3091&p=6

Barely faster??


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 Post subject: Re: Finally an image of Shanghai
PostPosted: Tue Mar 04, 2008 8:52 pm 
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Joined: Sun Sep 09, 2007 4:21 pm
Posts: 13
Alberto wrote:
Shanghai cache seems larger than expected IMO, the whole chip seems too large. Looks like 260/270 mm2

Alberto.


May seem so, but the cache sizes are confirmed here (and 1.648 V?):

Image


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 Post subject:
PostPosted: Tue Mar 04, 2008 9:03 pm 
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Joined: Tue Aug 07, 2007 4:54 am
Posts: 40
OK maybe I exaggerated a wee bit...ok alot :D

I think I fell for the hype and was expecting Barcelona to trump Core 2.. Not that I'm an AMD droid mind you. I just don't want Intel dominating performance too much; although it seems thats the way it's going at the moment.

Paul DeMone wrote:

I wouldn't expect much of a frequency boost from AMD's 45 nm process
however this will be AMD's second crack at this microarchitecture so they
should be able to squeeze critical paths based on their experience with
the original 65 nm version.


Paul, can you clarify what you mean by "squeeze critical paths?"


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 Post subject:
PostPosted: Tue Mar 04, 2008 9:20 pm 
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Joined: Wed Aug 29, 2007 3:55 pm
Posts: 800
Location: Great white north
Carfax wrote:
Paul, can you clarify what you mean by "squeeze critical paths?"


Manually improve (i.e. reduce overall circuit and wire delay) logic paths
within the CPU core that limit clock frequency.


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 Post subject: Re: Finally an image of Shanghai
PostPosted: Tue Mar 04, 2008 9:29 pm 
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Joined: Tue Sep 04, 2007 4:40 pm
Posts: 121
EaS wrote:

May seem so, but the cache sizes are confirmed here (and 1.648 V?)


CPU-z can't read Vcore correctly with Shanghai.
Today officials (AMD) said that 45nm chips would consume 15% less energy(even tho they feature 3x more L3 cache,so it's not a straight die shrink from 65nm) than 65nm parts,i presume per same clock.This explains the HKEPC slide claiming TDP drop from 125 to 95W for top speed bins(65nm-> 45nm).


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 Post subject:
PostPosted: Wed Mar 05, 2008 12:23 am 
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Joined: Sat Oct 06, 2007 11:35 am
Posts: 41
AMD Ships 45-Nano Shanghai, Deneb Chips :D
http://www.informationweek.com/news/sho ... =206901459


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