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Why has AMD decided to go all of a sudden for six cores (Instanbul) instead of eight (Montreal). Seems like a counterproductive measure to me? I means that they won't have anything to compete with an 8 core Nehalem chip in 2009.
Of course, it will be nice to put it against Dunnington. But I have this funny feeling that Dunnington will not be Intel's best chip....it seems like a brute force approach.
Quite contrary to me looks like productive measure: instead of four and eight core Montreals AMD will offer 6 and 12 cores Sao Paolos (Istanbul is somehow mid-term solution to this course)
Why has AMD decided to go all of a sudden for six cores (Instanbul) instead of eight (Montreal). Seems like a counterproductive measure to me? I means that they won't have anything to compete with an 8 core Nehalem chip in 2009.
Of course, it will be nice to put it against Dunnington. But I have this funny feeling that Dunnington will not be Intel's best chip....it seems like a brute force approach.
It's probably not a bad idea for AMD to take advantage of their relatively
small core size. At 45nm it can cram two cores (with 256 kB L1 total) into
30mm2. A single Nehalem core with 256 kB L2 also occupies ~30 mm2.
So in terms of IPC/mm2 you get two cores against one core with 2 threads.
The 8 core Nehalem seems to be a megamacholomaniamonolitic die.
larger still as Dunnington (700 mm2 ?) More for bragging rights
purpose as for profitability, considering that it will be rather TDP limited.
Istanbul could be at or just below 300 mm2. Istanbul/Sao Paulo should
become a mass market 32nm device so it's not a bad idea in terms of
risk reduction to develop them as server/workstation chips at 45nm.
It is better to add cores, to 6 in total, as to extend the L2 caches from
512kB to 1MB per core on a 4-core device as was planned with Montreal.
Why has AMD decided to go all of a sudden for six cores (Instanbul) instead of eight (Montreal). Seems like a counterproductive measure to me? I means that they won't have anything to compete with an 8 core Nehalem chip in 2009.
Of course, it will be nice to put it against Dunnington. But I have this funny feeling that Dunnington will not be Intel's best chip....it seems like a brute force approach.
It's probably not a bad idea for AMD to take advantage of their relatively small core size. At 45nm it can cram two cores (with 256 kB L1 total) into 30mm2. A single Nehalem core with 256 kB L2 also occupies ~30 mm2.
So in terms of IPC/mm2 you get two cores against one core with 2 threads.
The 8 core Nehalem seems to be a megamacholomaniamonolitic die. larger still as Dunnington (700 mm2 ?) More for bragging rights purpose as for profitability, considering that it will be rather TDP limited.
Istanbul could be at or just below 300 mm2. Istanbul/Sao Paulo should become a mass market 32nm device so it's not a bad idea in terms of risk reduction to develop them as server/workstation chips at 45nm.
It is better to add cores, to 6 in total, as to extend the L2 caches from 512kB to 1MB per core on a 4-core device as was planned with Montreal.
Regards, Hans
Perf = IPC x Clock
TDP = TDP_Core_atMHz*Ncores + TDP_accesories
The problematic is the Mhz per core equation of the TDP. MIPS efficency per watt at load is more important than anything else, Core size only matter at manufactoring time, TDP is your real issue, and efficency of the core is what make large core number possible.
The Core efficency at load is what will define your capability to make higher number of cores.
idle power is irrelevant when it comes to many cores.
How will the recent revelation about power consumption and per CPU load play out in these 6- and 12- core designs? Can AMD power down/hibernate multiple cores effectively while running one at full load? If its hard coded this could be good for servers. On the other hand the home consumer would freak on that setup.
Btw, according to this article (and others IIRC), Istanbul will have three HT links, while Sao Paolo will have four.
That is for the SKU. The die will most likely have four links, just like Barcelona, but something is either broken or left unexploited.
By the way, thanks to mas pointing it to me, I see that AMD claims that they will transition to 3xccHT3 on Socket F in late 2008, with Shanghai. Before that, the plan was to go to ccHT3 with the transition to the new socket (G34 or whatever it is called), and if true, this is good news. On the other hand, the new socket gets delayed, which means that Istanbul will be bandwidth deficient compared to competitive offerings from Intel (bad for HPTC) and that 4-and 8-socket single-hop topology will also have to wait (bad for commercial workloads).
Short summary: Socket G3 is dead, replaced by Socket G34 with whopping 1974 pins; differences presumably Quad channel DDR3 instead of dual channel DDR3.
Quad channel DDR3... We can expect some interesting PCB layouts form that. Opteron might well be forced to use more expensive PCB than Tukwila have to use.
Joined: Thu Jul 26, 2007 9:09 pm Posts: 18 Location: Arnhem, Gelderland, The Netherlands, Europe
[quoteQuad channel DDR3... quote]What is the use of a quad channel DDR3 as the Phenom core can't utilize the full bandwith of dual channel DDR2. For a six-core 10th generation processor, dual channel DDR3 should suffice in bandwidth.
I can see one reason to go to a quad channel system. That would be to use to processors on one package, link them using HT (with the possibility of a very high clock) and bring let each of the processors memory controller controle 2 channels. 2 x 2 channels per processor = 4 channels
Short summary: Socket G3 is dead, replaced by Socket G34 with whopping 1974 pins; differences presumably Quad channel DDR3 instead of dual channel DDR3.
This looks better, Instead of throttling memory bandwidth and amount by cramming two processors in a previous generation package it's better to introduce a next generation package early by using two dies.
Opteron wrote:
Seems strange on the first view (rectangular), however 2 DIEs should fit perfectly.
cheers, Opteron
A rectangular size reduces the number of motherboard layers which
critically depends on how many vias a signal from the innermost
signal pins/balls has to pass to get at the outside.
[quoteQuad channel DDR3... quote]What is the use of a quad channel DDR3 as the Phenom core can't utilize the full bandwith of dual channel DDR2. For a six-core 10th generation processor, dual channel DDR3 should suffice in bandwidth.
I can see one reason to go to a quad channel system. That would be to use to processors on one package, link them using HT (with the possibility of a very high clock) and bring let each of the processors memory controller controle 2 channels. 2 x 2 channels per processor = 4 channels
Jeschael
Apparently Magny-Cours will be on G34, and it will have 12 cores (well, 2 x 6) and probably reach frequencies in the area of 3 GHz or more. So yeah, 2 DDR2 channels are enough for 4 cores at 2.5 GHz, but 12 --- probably slightly more efficient --- cores at 3 GHz+?
Plus, that may not be the case for Magny-Cours, but future designs on the same socket will probably have some form of SMT and even more cores... So we might be looking at 32 threads or more. I don't think going for 4 DDR3 channels is overdoing it.
I wonder if AMD found some kind of critical mass of their cores scales better and sums of three were it. The fourth core may be too large of penalty for shared cache coherency or something.
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