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 Post subject: Real CPU production cost
PostPosted: Mon Apr 28, 2008 2:19 pm 
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Joined: Mon Apr 28, 2008 1:53 pm
Posts: 8
This is a very interesting topic to me.

From what I can gather, once mature, the cost increase to move to a lower tech is very roughly up to 20% extra.

References from AMD & Intel often list taking R&D for fab & chip costs, writeoffs, construction etc into account & land much higher than same tech price from IE TSMC & other foundries. Where their listed price as I gather, is basically the cost for having the wafers run through the fab, without mask. Packaging, error checking included in wafer price generally?

Seen several price references for >$3K for 90 nm & $3k-$3,6K for 65 nm. But these are medium to semi-high quantities. AMD & Intel own their own fab, for two reasons. Tweak the fab to their exact needs & lower price/higher margins, surely they must be getting far better prices on their wafers when done than if they went to another foundry. But how much better?

My interest mainly lies in mature tech, ie not test & new tech's as 45nm for amd when it goes online, although that is interesting also.

http://www.tgdaily.com/content/view/36795/118/
One of a few covering idf giving a reference of roughly $10k per 45nm Atom wafer, which seems very high?

http://forum.beyond3d.com/showthread.php?t=41816
References for GPU die & packaging cost. Some interesting comments.

"I sit in a TSMC info session basically meant to push people to upgrade from 90nm to 65nm."
"According to them, the speed increment is about 15% in general and costs about 15% more."
"The wafer cost is about 3k (after volume discount and technology development agreement, etc)."

http://www.ocforums.com/showthread.php?t=550542
Great thread by JCLW. Only listing
5,3K for 65nm AMD wafer? Seems high?
$4900 Intel wafer, no separation 45/65nm, way out of line with 10K. Yield even higher? IE cache security, X3 etc?

"Assuming:
0.002 Defects per mm^2
$4900 per 300mm CMOS Wafer
$5300 per 300mm SOI Wafer
$2700 per 200mm SOI Wafer
alpha of 1
Dies Per Wafer = {[pi * (Wafer Diameter/2) ^ 2] / Die Area} - {[pi * Wafer Diameter] / (2 * Die Area) ^ 1/2}
Yield = (1 + [Defects per Area * Die Area / alpha]) ^ (-alpha)
$10 burning, binning and packaging cost for single die chips
$15 burning, binning and packaging cost for dual die chips"



CPU yield, wafer costs on different tech, industry trend (ie price increases for every shrink, seen both TSMC, TI & others mention 1,15-1,2x) & any thoughts on real costs for CPU dies, packaging etc would be of interest. JCLW's post is the only one I have seen on for burning, binning & packaging, especially on multi die chips. How far from target is he?


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 Post subject:
PostPosted: Mon Apr 28, 2008 3:24 pm 
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Joined: Wed Aug 29, 2007 3:55 pm
Posts: 1006
Location: Great white north
Wafer cost depends on multiple factors. One of the biggest factors
is the number of metal layers. Each extra layer adds a few hundred
dollars per wafer. IIRC at 65 nm Intel uses 8 metal layers and AMD
uses 12. Another factor is bulk vs SOI. Using SOI probably adds a
few hundred extra dollars from higher blank wafer costs and likely
somewhat lower line yield (i.e. more scrapped wafers). A big factor
in comparing processed wafer cost of Intel vs anyone else making
MPUs is volume. Intel spins many times more logic process wafers
each week than anyone else. This gives Intel tremendous economy
of scale in negotiating prices for supplies. AMD is probably at a non
trivial labour cost disadvantage vs Intel because its main fab is in
Germany. Factor this all together and IMO Intel enjoys a sizable
processed wafer cost advantage over AMD even when comparing
mainstream production across feature size generations (i.e. 45 nm
for Intel vs 65 nm for AMD).

Now you come to yield. AMD once again loses because of its use
of SOI and 4 extra layers of metal and lower production volumes.
Economy of scale also reduces Intel's test and packaging costs.

Is there any support for all of this theorizing? Intel's recent reports
to analysts show that its wafer production is split roughly equally
three ways between MPUs, chipsets, and "other" (flash). The margin
on MPUs is high and low for on chipsets and other. Nearly all of AMD's
wafer production is for MPUs. In their most recent earnings report
Intel said its overall gross margin was 53.8% while AMD said its
gross margin was 42%. Intel's margin just for its processors was
probably in the 80% range (to average out its overall margin to
53.8%) or nearly twice AMD's MPU margin.


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 Post subject:
PostPosted: Mon Apr 28, 2008 3:33 pm 
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Joined: Mon Apr 28, 2008 1:53 pm
Posts: 8
Well, any & all arguments will compare apples & oranges ^^ But as for CPU margin, which CPU's do we talk about? According to Fudzilla quoting Mercury research, 96,6% av all CPU's sold are in the sub $200 segment, as to why a celeron will have "vastly" lower margin than a monster quad code, no suprise there... also take into account the same die with different speeding bins giving different margins on the same part. All making it much harder or near impossible to make some estimate on wafer & production cost out of their earning report. If they had 1 SKU it would be rather easy ^^


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 Post subject:
PostPosted: Mon Apr 28, 2008 3:59 pm 
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Joined: Fri Aug 17, 2007 2:55 pm
Posts: 369
Won't ASP and gross margin give a reasonable estimate of the average cost of producing a finished CPU, simply because 3/4 of Intel's revenue is based on CPUs.

You should also be able to bound that average cost of production by assuming either 0 margin on the 1/4 that is not CPUs, or by assuming that the GM on all products is the same (i.e. the GM on CPUs is the same as chipsets, motherboards and other).


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 Post subject: Yes & no
PostPosted: Mon Apr 28, 2008 4:09 pm 
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Joined: Mon Apr 28, 2008 1:53 pm
Posts: 8
It will, sort of. But which one? Largest part is sub 200 CPU's as said, by a long shot. But we have multi K Itanium's, Sky priced Xeons which have "b i g" margins attached to them. Celerons etc have low low margins compared. So, ok, we have a ASP & average gross margin, what die size & node size are we to calculate it all on to get a wafer price? Anyone know ASP for intel/amd btw? Only seen it in reference to up/down in quarter report references. Margins I've seen though.


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 Post subject: Re: Yes & no
PostPosted: Mon Apr 28, 2008 5:47 pm 
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Joined: Wed Aug 29, 2007 3:55 pm
Posts: 1006
Location: Great white north
LarsJurgen wrote:
Anyone know ASP for intel/amd btw? Only seen it in reference to up/down in quarter report references. Margins I've seen though.


http://www.investorvillage.com/smbd.asp ... id=3935327

These figures are reportedly from Mercury Research. They look legit.

4Q07 ASP

Intel
server $415
desktop $96
mobile $109

AMD
server $297
desktop $56
mobile $63


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 Post subject:
PostPosted: Mon Apr 28, 2008 5:48 pm 
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Joined: Wed Aug 29, 2007 3:55 pm
Posts: 1006
Location: Great white north
TacoBell wrote:
Won't ASP and gross margin give a reasonable estimate of the average cost of producing a finished CPU, simply because 3/4 of Intel's revenue is based on CPUs.

You should also be able to bound that average cost of production by assuming either 0 margin on the 1/4 that is not CPUs, or by assuming that the GM on all products is the same (i.e. the GM on CPUs is the same as chipsets, motherboards and other).


Keep in mind you can have negative margins - products sold at a loss.
Like Intel's flash business ("other") for example.


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 Post subject:
PostPosted: Tue Apr 29, 2008 12:38 am 
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Joined: Fri Nov 02, 2007 12:19 pm
Posts: 60
Paul DeMone wrote:
Now you come to yield. AMD once again loses because of its use
of SOI and 4 extra layers of metal and lower production volumes.
Economy of scale also reduces Intel's test and packaging costs.

Upper-level metallization accounts for an insignificant fraction of defects on integrated circuits. Intel's LGA packages require a more complex build-up process than conventional pin-based packages.


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 Post subject: DDR/2 tech & cost?
PostPosted: Tue Apr 29, 2008 1:17 am 
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Joined: Mon Apr 28, 2008 1:53 pm
Posts: 8
Considering the low margin on memories & flash I was considering going backwards, but the numbers I ended up with makes no sense whatsoever. I know flash & ddr gain from vast quantities & "same" design, ie not several different gpu/cpu core designs, but still so far away I fear even to list it ^^

ddr2 die mm2 on google gives lots on numbers of die size for ddr2.
Is the wafer run cost vastly lower for nand flash & ddr/2 than for other cmos wafers?

http://www.techonline.com/product/under ... /193100404
http://www.semiconductor.com/resources/ ... p?pid=4168
Just to list 2.


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 Post subject:
PostPosted: Tue Apr 29, 2008 1:51 am 
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Joined: Wed Aug 29, 2007 3:55 pm
Posts: 1006
Location: Great white north
slacker wrote:
Paul DeMone wrote:
Now you come to yield. AMD once again loses because of its use
of SOI and 4 extra layers of metal and lower production volumes.
Economy of scale also reduces Intel's test and packaging costs.

Upper-level metallization accounts for an insignificant fraction of defects on integrated circuits. Intel's LGA packages require a more complex build-up process than conventional pin-based packages.


It isn't the the upper level metalization that is the issue here. It is the
extra four layers that AMD uses compared to Intel. That represents
at least eight more lithographic steps and every extra processing
step introduces an opportunity for defects to come in.

Something I didn't mention before is that the extra processing steps
means longer processing time in the fab and reduced fab throughput
which itself increases processed wafer cost.


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 Post subject: Re: Real CPU production cost
PostPosted: Tue Apr 29, 2008 2:38 am 
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Joined: Mon Mar 10, 2008 10:42 pm
Posts: 30
LarsJurgen wrote:
This is a very interesting topic to me.

From what I can gather, once mature, the cost increase to move to a lower tech is very roughly up to 20% extra.



What a very good Pauling Point to start your post with.

For the some 10 nodes (0.5um -> 32nm) that I was involved with at TI we had an operating expectation of not exceeding 20% incremental costs for wafer-outs on each successive node for the qualifying product of the node (which was always a shrink of some product from the prior node, kind of like an unpublished tic-toc I guess).

We had one node that had problems meeting this cost budget (meaning it came in at >20% cost adder)...our 90nm node no thanks to going with single-damascene integration for the lowest 4 metal levels.

Of course we'll never know if 45nm or 32nm would have ever met their cost targets either...TSMC FTW.


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 Post subject: Re: Yes & no
PostPosted: Tue Apr 29, 2008 2:56 am 
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Joined: Fri Oct 05, 2007 7:46 am
Posts: 167
Paul DeMone wrote:
LarsJurgen wrote:
Anyone know ASP for intel/amd btw? Only seen it in reference to up/down in quarter report references. Margins I've seen though.


http://www.investorvillage.com/smbd.asp ... id=3935327

These figures are reportedly from Mercury Research. They look legit.

4Q07 ASP

Intel
server $415
desktop $96
mobile $109

AMD
server $297
desktop $56
mobile $63


Having read the MR report, I can vouch these are legit.


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 Post subject:
PostPosted: Tue Apr 29, 2008 4:51 am 
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Joined: Fri Nov 02, 2007 12:19 pm
Posts: 60
Paul DeMone wrote:
It isn't the the upper level metalization that is the issue here. It is the
extra four layers that AMD uses compared to Intel. That represents
at least eight more lithographic steps and every extra processing
step introduces an opportunity for defects to come in.

The upper-level metallization is precisely the issue here. Each time AMD adds an extra metal layer or four to their process, they are additions to the top of the metal stack rather than the bottom. In other words, they're adding thick and fat wires at the top rather than narrow and thin ones at the bottom. The top metal layers account for virtually no defects because they're easy to fabricate (large), and fault-resistant (plenty of redundant vias, difficult to short-circuit adjacent wires).

Quote:
Something I didn't mention before is that the extra processing steps
means longer processing time in the fab and reduced fab throughput
which itself increases processed wafer cost.

While any additional process steps will add to manufacturing costs, there is no necessary consequence of reduced throughput. Not only can you pipeline microprocessors, but you can also pipeline the manufacturing process.


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 Post subject:
PostPosted: Tue Apr 29, 2008 8:59 am 
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Joined: Mon Apr 28, 2008 1:53 pm
Posts: 8
If <20% per shrink is realistic (seen references of that & lower for TI, TSMC & others) & 300mm TSMC 90nm at the time of G80 cost $3k. Should that not translate to

64nm = 3K x 1,2 = 3600
45nm = 3,6K x 1,2 = 4320

I don't care what anyone tells me, be it intel rep & the reasons, I refuse to believe Intel is paying "more" than list price to customers for TSMC, although large ones, by a large margin. AMD is another story with SOI (How is SOI scalable? sub 32nm? Or just 90-45?). Surely 10k listed from Intel must be some form of creative accounting or strange sumup, IE including all dev, research, mask costs etc & dividing it by made wafers to date? IE saying a new line of subs cost $3 billion every mile (for the first mile for the first sub.)

BTW, TSMC & other foundries, is error checking, binning, fusing & mounting included in price? If not, how big a part is that? Is he far away from reality in his estimate?


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 Post subject:
PostPosted: Tue Apr 29, 2008 12:17 pm 
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Joined: Mon Mar 10, 2008 10:42 pm
Posts: 30
slacker wrote:
Paul DeMone wrote:
Something I didn't mention before is that the extra processing steps
means longer processing time in the fab and reduced fab throughput
which itself increases processed wafer cost.

While any additional process steps will add to manufacturing costs, there is no necessary consequence of reduced throughput. Not only can you pipeline microprocessors, but you can also pipeline the manufacturing process.


This can only be true if the fab's WIP capacity (work in progress) is increased commensurate with the reduced cycle-time for wafer start ot wafer out.

It's pretty difficult to beat 1 day per mask level in a commercially viable approach...so if you add a metal level you can't really avoid adding 2 or 3 days to the total cycle time.

An 11LM device (65nm) will take about 70days to meander thru a fab on a good cycle, 80 or 90 days would be more typical, but going from 70 to 73 days in going from 11 to 12ML would reduce the fab wafer outs by ~4% unless the fab was expanded in capacity to handle a WIP increase of ~4%.

And that's best case, we more typically see 2-3 days per mask level at 65nm across the logic IDM's for your standard priority lots. Adding a metal level in these situations can decrease your wafer outs by 10%...it isn't such a small issue. I remember our 65nm qual device was changed last minute (from an R&D perspective) from a 5LM to 6LM device (big thick copper leads, microns, for the 6th level of metal)...defect density was not so much the issue but the cycle-time adder was not making anyone happy.


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