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 Post subject: SSE5
PostPosted: Thu Aug 30, 2007 8:22 am 
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Joined: Wed Jun 27, 2007 1:38 pm
Posts: 668
AMD has released SSE5 specifications: http://developer.amd.com/sse5.jsp

new instructions include:
Fused multiply accumulate (FMACxx) instructions
Integer multiply accumulate (IMAC, IMADC) instructions
Permutation and conditional move instructions
Vector compare and test instructions
Precision control, rounding, and conversion instructions


I wonder if AMD can really call these new instruction "SSE5"?


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 Post subject:
PostPosted: Thu Aug 30, 2007 8:28 am 
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Joined: Tue Aug 07, 2007 4:54 am
Posts: 40
I thought FMAC was not possible on x86?


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 Post subject:
PostPosted: Thu Aug 30, 2007 8:38 am 
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Joined: Tue Aug 07, 2007 2:04 pm
Posts: 126
Location: Tampere, Finland
Carfax wrote:
I thought FMAC was not possible on x86?


MAC does not fit into the default instruction format, where each instruction has only 2 operands (destination = op(destination, source)) but by making the instruction decoder more complex then can use other instruction format also. They introduced some new prefix byte for this.


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 Post subject:
PostPosted: Thu Aug 30, 2007 8:39 am 
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Joined: Tue Aug 07, 2007 2:04 pm
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Location: Tampere, Finland
But the big question is:

Are these implemented in K10 or only in the future like barcelona's 45nm shrink?


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 Post subject:
PostPosted: Thu Aug 30, 2007 9:12 am 
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Joined: Wed Jun 27, 2007 1:38 pm
Posts: 668
Neither. Beyond3d is reporting that SSE5 will be implemented in Bulldozer core in 2009.


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 Post subject:
PostPosted: Thu Aug 30, 2007 12:33 pm 
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Joined: Thu Aug 09, 2007 2:51 pm
Posts: 9
Will they also include the real SSE4 in that core?


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 Post subject: Re: SSE5
PostPosted: Thu Aug 30, 2007 2:35 pm 
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Joined: Wed Aug 29, 2007 3:55 pm
Posts: 1006
Location: Great white north
jack wrote:
AMD has released SSE5 specifications: http://developer.amd.com/sse5.jsp

new instructions include:
Fused multiply accumulate (FMACxx) instructions
Integer multiply accumulate (IMAC, IMADC) instructions
Permutation and conditional move instructions
Vector compare and test instructions
Precision control, rounding, and conversion instructions


I wonder if AMD can really call these new instruction "SSE5"?


You forgot to mention the addition of three address instructions.

A quarter century after RISC design principles were introduced to
the industry x86 is still trying to bridge the gap.


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 Post subject:
PostPosted: Thu Aug 30, 2007 3:46 pm 
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Joined: Wed Jun 27, 2007 1:45 pm
Posts: 59
Location: Germany
xMartin wrote:
Will they also include the real SSE4 in that core?

Image

so the answer seems to be "no" ...


(funny, this doesn't seem to work:
Image
bad url parsing it seems :-/ )


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 Post subject:
PostPosted: Thu Aug 30, 2007 5:45 pm 
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Joined: Tue Aug 07, 2007 4:54 am
Posts: 40
But, if Bulldozer is going to have SSE5, I assume that it wouldn't even need SSE4 as SSE5 would be far superior would it not?


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 Post subject:
PostPosted: Thu Aug 30, 2007 6:20 pm 
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Joined: Mon Jul 23, 2007 1:48 am
Posts: 81
looking at past history, amd has implemented mmx, sse, sse2, sse3, and ssse3 (pretty sure it will be in barcelona. i don't see why this would change for sse4.

it'll be interesting to see if intel implements sse5 as amd is calling it. i don't think intel has implemented anything instruction from amd, or at least very few.


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 Post subject:
PostPosted: Thu Aug 30, 2007 6:50 pm 
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Posts: 68
cornelius785 wrote:
looking at past history, amd has implemented mmx, sse, sse2, sse3, and ssse3 (pretty sure it will be in barcelona. i don't see why this would change for sse4.

it'll be interesting to see if intel implements sse5 as amd is calling it. i don't think intel has implemented anything instruction from amd, or at least very few.


Uh, it's called AMD64.


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 Post subject:
PostPosted: Thu Aug 30, 2007 7:51 pm 
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Joined: Mon Jul 23, 2007 1:48 am
Posts: 81
i was talking more about SIMD-like instructions. my understanding of AMD64 (or whatever you want to call it) adds new registers, extends existing onesc, and creation of a prefix to access the extended registers. i'd call that different from adding SIMD capablities to x86. maybe i just worded my statement wrong.


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 Post subject:
PostPosted: Fri Aug 31, 2007 10:09 am 
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Joined: Wed Jun 27, 2007 1:38 pm
Posts: 668
Anandtech says that AMD will not support SSE4 until 2010 at earliest: "Finally, we've been told that full SSE4 support is coming for AMD's chips, but without a date. We know that it won't be in Bulldozer, which means SSE4 support won't be happening until a Bulldozer refresh, which will be no earlier than 2010."

http://www.anandtech.com/cpuchipsets/sh ... spx?i=3073


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 Post subject:
PostPosted: Fri Aug 31, 2007 10:13 am 
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Joined: Mon Aug 13, 2007 12:04 pm
Posts: 84
Well, the chinese CPU-Z pictures showed SSE4A support, for what it's worth....


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 Post subject:
PostPosted: Fri Aug 31, 2007 10:42 am 
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Joined: Wed Jun 27, 2007 1:07 am
Posts: 26
Location: Amsterdam
Richard Van Den Boom wrote:
Well, the chinese CPU-Z pictures showed SSE4A support, for what it's worth....


SSE4A is a subset of SSE4.


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