Aceshardware

AMD has released SSE5 specifications: http://developer.amd.com/sse5.jsp

new instructions include:
Fused multiply accumulate (FMACxx) instructions
Integer multiply accumulate (IMAC, IMADC) instructions
Permutation and conditional move instructions
Vector compare and test instructions
Precision control, rounding, and conversion instructions


I wonder if AMD can really call these new instruction "SSE5"?

I thought FMAC was not possible on x86?

MAC does not fit into the default instruction format, where each instruction has only 2 operands (destination = op(destination, source)) but by making the instruction decoder more complex then can use other instruction format also. They introduced some new prefix byte for this.

But the big question is:

Are these implemented in K10 or only in the future like barcelona's 45nm shrink?

Neither. Beyond3d is reporting that SSE5 will be implemented in Bulldozer core in 2009.

Will they also include the real SSE4 in that core?

You forgot to mention the addition of three address instructions.

A quarter century after RISC design principles were introduced to
the industry x86 is still trying to bridge the gap.

so the answer seems to be "no" ...


(funny, this doesn't seem to work:

bad url parsing it seems :-/ )

But, if Bulldozer is going to have SSE5, I assume that it wouldn't even need SSE4 as SSE5 would be far superior would it not?

looking at past history, amd has implemented mmx, sse, sse2, sse3, and ssse3 (pretty sure it will be in barcelona. i don't see why this would change for sse4.

it'll be interesting to see if intel implements sse5 as amd is calling it. i don't think intel has implemented anything instruction from amd, or at least very few.

Uh, it's called AMD64.

i was talking more about SIMD-like instructions. my understanding of AMD64 (or whatever you want to call it) adds new registers, extends existing onesc, and creation of a prefix to access the extended registers. i'd call that different from adding SIMD capablities to x86. maybe i just worded my statement wrong.

Anandtech says that AMD will not support SSE4 until 2010 at earliest: "Finally, we've been told that full SSE4 support is coming for AMD's chips, but without a date. We know that it won't be in Bulldozer, which means SSE4 support won't be happening until a Bulldozer refresh, which will be no earlier than 2010."

http://www.anandtech.com/cpuchipsets/sh ... spx?i=3073

Well, the chinese CPU-Z pictures showed SSE4A support, for what it's worth....

SSE4A is a subset of SSE4.