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Joined: Tue Aug 07, 2007 2:04 pm Posts: 126 Location: Tampere, Finland
I thought FMAC was not possible on x86?
MAC does not fit into the default instruction format, where each instruction has only 2 operands (destination = op(destination, source)) but by making the instruction decoder more complex then can use other instruction format also. They introduced some new prefix byte for this.
i was talking more about SIMD-like instructions. my understanding of AMD64 (or whatever you want to call it) adds new registers, extends existing onesc, and creation of a prefix to access the extended registers. i'd call that different from adding SIMD capablities to x86. maybe i just worded my statement wrong.
Anandtech says that AMD will not support SSE4 until 2010 at earliest: "Finally, we've been told that full SSE4 support is coming for AMD's chips, but without a date. We know that it won't be in Bulldozer, which means SSE4 support won't be happening until a Bulldozer refresh, which will be no earlier than 2010."
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