Aceshardware

Any chip designing expert says that it is a very bad and risky practice developing a brand new architecture on a brand new node. AMD promises us the brand new bulldozer core on 32nm node.
Does it mean that AMD has broken the rules and started the gambling in rush to reach Intel?
or Does it mean that Interlagos and Valencia just a shrink of the old good Opteron and AMD are fooling us again?

I am puzzled.

Maybe, or maybe they have no money to make a new core and then make a die shrink of it so try to make it right on the new process.


My bet is it won't be just a shrink of the processors we have today but will be based on them.

It just means that because bulldozer is so much delayed, they deciced to skip the 45nm bulldozer because they can manufacture 32nm bulldozer at same time frame.

(originally bulldozer was supposed to be out 2009H2)


edit: whoops, replied to my own message instead editing it..

It could be a business to bet the chances of Bulldozer.
My bet is we will not see Bulldozer (like a brand new architecture) in 2011.

You are wrong. Bulldozer is a brand new design.And it is a Q1/Q2 2011 launch.

I will be happy to see it, but i comfirm my bet - we will not see it in 2011.

And i say again-you are wrong. You can "comfirm" whatever you like,it won't change a thing.

There will be 32nm Phenom core, at least for notebooks: http://www.fudzilla.com/content/view/15809/1/

I'm confident, that AMD will manage to have the 32 nm Bulldozer core in Interlagos/Valencia ready in 2011. Their original plan was to have this core appear in 2009 as 45 nm MPU. Some of the possible reasons for the change (too much power consumption at 45 nm, die size too large at 45 nm, inclusion of AVX, too complex core needing more testing or development) could actually mean, that in these cases finishing the design in 45 nm could have produced a not that competitive MPU (e.g. fast, but too expensive to produce, too hot, missing relevant capabilities like AVX), but there was a chance to have something in hands already in 2009 having the planned architecture, but in the need of some tuning or extension with at least 15 months of additional time for that. So I don't see it as being the same complexity and risk as planning a 45 nm MPU for 2009 and switching to 32 nm also in 2009.

Some more speculation: Especially adding AVX compatible extensions instead of SSE5 could have led them to extend the FPU width to 256 bit or skip the 45 nm 128 bit wide FPU (in favor of an already planned 256 bit wide FPU in 32 nm). AVX compatibility also requires some redesign regarding the FP register files.

You can read more of my thoughts (well not covering exactly this topic ;)) on my blog.

At least Q1/Q2-2011 is already missed.

I think they will be limited in Frequency, because the complexity of the cluster dispatcher between the Ints and float part, and the OOO. 2.6Ghz will be a challenge if you want good IPC.
They can choose to sacrify latency of FP and try to go for thoughput computing, but then, they ll be very slow at most of the x87/SSEx.x related performance tests. If I was them, i would put a PLL and some multiplier between the ints/OOO and the FP cluster, you don't want to be limited in INT performance because your FP cluster dispatcher can't crank up frequency.
The FPU dispatcher will be a serious hot spot in the middle, causing a lot discipation. Let's see if they can solve this one, my job is always more fun when they do something challenging.
Just my 2 cents ...
This is my personal opinion, I never represent my employeer in this forum.

This thing has been in development 6+ years and was originally targeted at 45nm node.Now that they delayed it to 32nm node i seriously doubt they will be power/frequency limited,and especially at 2.6Ghz. The design is scalable and can vary in number of "cores"(superclusters) and will go from 4 to 8 for non MCM desktop parts and double that for MCM server ones. I'm really interested in seeing how much efficiency they managed to gain in singlethreaded code with their cluster approach(CMT),should be quite a big step up. SSE part will be AVX 256b compatible so i suppose this will be on par with sandyb. SSE capabilities.Also multithread performance of bulldozer should naturally be a step up as well,with kinda a hybrid mode of 2 clusters sharing one FPU( a la SMT).

Sometimes beautiful babies take time to develop. Nehalem started in 2003 IIRC.

Beautiful or not babies always take 9 months.